公开(公告)号：US20240347464A1

公开(公告)日：2024-10-17

申请号：US18752525

申请日：2024-06-24

Applicant: Micron Technology, Inc.

Inventor： Lingyu Kong ,  Lifang Xu ,  Indra V. Chary ,  Shuangqiang Luo ,  Sok Han Wong

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/562 ,  H10B41/27 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising insulative structures vertically interleaved with conductive structures, first support pillar structures vertically extending through the stack structure in a first staircase region including steps defined at edges of tiers of the insulative structures and conductive structures, and second support pillar structures vertically extending through the stack structure in a second staircase region including additional steps defined at edges of additional tiers of the insulative structures and conductive structures, the second support pillar structures having a smaller cross-sectional area than the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20240297269A1

公开(公告)日：2024-09-05

申请号：US18664203

申请日：2024-05-14

Applicant: Micron Technology, Inc.

Inventor： Scott D. Schellhammer ,  Scott E. Sills ,  Lifang Xu ,  Thomas Gehrke ,  Zaiyuan Ren ,  Anton J. De Villiers

IPC: H01L33/24 ,  H01L33/00 ,  H01L33/16 ,  H01L33/22 ,  H01L33/32

CPC classification number: H01L33/24 ,  H01L33/007 ,  H01L33/16 ,  H01L33/22 ,  H01L33/32

Abstract: Light emitting diodes and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode (LED) includes a substrate, a semiconductor material carried by the substrate, and an active region proximate to the semiconductor material. The semiconductor material has a first surface proximate to the substrate and a second surface opposite the first surface. The second surface of the semiconductor material is generally non-planar, and the active region generally conforms to the non-planar second surface of the semiconductor material.

公开(公告)号：US20240284672A1

公开(公告)日：2024-08-22

申请号：US18443013

申请日：2024-02-15

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Matthew J. King ,  Indra V. Chary ,  Yoshiaki Fukuzumi ,  Lifang Xu ,  Paolo Tessariol ,  Shuangqiang Luo

IPC: H10B43/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B43/10

Abstract: Methods, systems, and devices for merged cavities for conductor formation in a memory die are described. An array of cavities may be formed through a stack of material layers of a memory die, and conductors may be formed at least in part by merging some of the cavities of the array. Such cavities may be sized in accordance with a relatively smallest feature that implements a subset of such cavities, and a smallest associated feature may be formed using a first subset of the array of cavities. Conductors may be formed at least in part by merging two or more cavities of a second subset of the array of cavities using a material removal operation to remove portions of the stack of material layers. Such merging may support conductors being formed with a cross-section that is greater than a cross-section of other features formed using such cavities that are not merged.

公开(公告)号：US20240071918A1

公开(公告)日：2024-02-29

申请号：US17822421

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Sidhartha Gupta ,  Indra V. Chary ,  Richard J. Hill ,  Umberto Maria Meotto

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5283 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A microelectronic device includes a stack structure having tiers each including conductive material vertically neighboring insulative material and conductive contact structures. The stack structure is divided into blocks horizontally extending in parallel in a first direction and separated from one another in a second direction orthogonal to the first direction by insulative slot structures. At least one of the blocks includes a lower stadium structure having steps including edges of some of the tiers, and an upper stadium structure vertically overlying the lower stadium structure and having additional steps including edges of some other of the tiers vertically overlying the some of the tiers. The additional steps have greater tread widths in the first direction than the steps. Conductive contact structures are in contact with the additional steps of the upper stadium structure of the at least one of the blocks. Memory devices and electronic systems are also described.

公开(公告)号：US20240071902A1

公开(公告)日：2024-02-29

申请号：US17893718

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Lifang Xu

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578

CPC classification number: H01L23/5226 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578

Abstract: Methods, systems, and devices for folded staircase via routing for memory are described. For instance, a memory device may include a set of word lines extending in first direction. Additionally, the memory device may include a first via, a second via, and a third via in a trench that extends through at least a portion of the set of word lines The first via, the second via, and the third via may extend in a second direction different than the first, where the second via is between the first via and the third via along the first direction, and where the second via is coupled with a word line of the set of word lines. Additionally, the first via and the third via may be electrically isolated from the word line of the set of word lines.

公开(公告)号：US11894305B2

公开(公告)日：2024-02-06

申请号：US17658907

申请日：2022-04-12

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53257 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20240029795A1

公开(公告)日：2024-01-25

申请号：US17868232

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Anna Maria Conti ,  Lifang Xu ,  Harsh Narendrakumar Jain

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Memory circuitry comprising strings of memory cells comprises channel-material strings of memory cells extending through insulative tiers and conductive tiers in a memory-array region. The insulative and conductive tiers extend from the memory-array region into a stair-step region. A plurality of stair-step structures is in the stair-step region. The stair-step structures individually comprise two opposing flights of stairs. The stair-step structures comprise an SGD stair-step structure and non-SGD stair-step structures. At least one of the non-SGD stair-step structures has less total stairs than are in individual of multiple others of the non-SGD stair-step structures. Other embodiments, including method, are disclosed.

公开(公告)号：US11744076B2

公开(公告)日：2023-08-29

申请号：US17824582

申请日：2022-05-25

Applicant: Micron Technology, Inc.

Inventor： Vinayak Shamanna ,  Lifang Xu ,  Aaron R. Wilson

IPC: H10B43/27 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5221 ,  H01L23/5283 ,  H01L23/53257 ,  H01L23/53295 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: Some embodiments include an integrated assembly having a memory array region, a staircase region, and an intervening region between the staircase region and the memory array region. The intervening region includes first and second slabs of insulative material extending through a stack of alternating insulative and conductive levels. Bridging regions are adjacent to the slabs. First slits are along the bridging regions, and second slits extend through the slabs. First panels are within the first slits, and second panels are within the second slits. The second panels are compositionally different from the first panels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230178488A1

公开(公告)日：2023-06-08

申请号：US17643061

申请日：2021-12-07

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Lifang Xu ,  Xiao Li ,  Jivaan Kishore Jhothiraman ,  Mohadeseh Asadolahi Baboli

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L27/11556

Abstract: A microelectronic device comprises stack structure comprising an alternating sequence of conductive material and insulative material arranged in tiers, and having blocks separated by dielectric slot structures. Each of the blocks comprises a stadium structure, a filled trench overlying the stadium structure, support structures extending through the filled trench and tiers of the stack structure, and dielectric liner structures covering sidewalls of the support structures. The stadium structure comprises staircase structures each having steps comprising edges of the tiers of the stack structure. The filled trench comprises a dielectric material interposed between at least two additional dielectric materials. The dielectric liner structures comprise first protrusions at vertical positions of the dielectric material, and second protrusions at vertical positions of the conductive material of the tiers of the stack structure. The second protrusions have greater horizontal dimensions than the first protrusions. Memory devices, electronic systems, and methods are also described.

公开(公告)号：US20230143406A1

公开(公告)日：2023-05-11

申请号：US18083412

申请日：2022-12-16

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  Justin B. Dorhout ,  Jian Li ,  Haitao Liu ,  Paolo Tessariol

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/76816 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.