公开(公告)号：US10248613B2

公开(公告)日：2019-04-02

申请号：US15402519

申请日：2017-01-10

Applicant: QUALCOMM Incorporated

Inventor： Yuval Corey Hershko ,  Lior Amarilio ,  Nir Strauss

IPC: G06F13/20 ,  G06F13/42

Abstract: Data bus activation in an electronic device is provided. In one aspect, a host circuit determines a cumulative potential representing a cumulative fractional bus activation vote on a data line(s) in the data bus. The host circuit activates the data bus when the cumulative potential is greater than a configurable bus activation threshold. In another aspect, a device circuit(s) determines a selected signal strength threshold that is less than determined signal strength of an incoming signal. Accordingly, the device circuit(s) asserts a fractional potential corresponding to the selected signal strength threshold on the data line(s) as a fractional bus activation vote in the cumulative fractional bus activation vote. By activating the data bus based on the cumulative fractional bus activation vote, the host circuit can support timely data bus activation while preventing the data bus from being falsely activated, thus improving robustness of data bus activation in the electronic device.

公开(公告)号：US20190087369A1

公开(公告)日：2019-03-21

申请号：US15709550

申请日：2017-09-20

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Syed Naseef ,  Ghanashyam Prabhu

IPC: G06F13/28 ,  G06F13/16 ,  G06F5/06 ,  G06F13/42 ,  G06F13/24

Abstract: Full-duplex memory access systems and methods for improved quality of service (QoS) are disclosed. In one aspect, a primary bus owner will evaluate an output from a secondary bus owner when the primary bus owner takes control of the bus to determine if the secondary bus owner has data to send to the primary bus owner and/or is in the midst of a bulk data transfer. If the evaluation determines that there is still data to be transferred, the primary bus owner may refrain from draining an internal register unless a full word is present in the register. By reducing memory access for a partial word in the register, QoS may be improved.

公开(公告)号：US20180196681A1

公开(公告)日：2018-07-12

申请号：US15402631

申请日：2017-01-10

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Sharon Graif ,  Oren Nishry

IPC: G06F9/44 ,  G06F13/364 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/404 ,  G06F13/364 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

Abstract: Selective processor wake-up in an electronic device is provided. In one aspect, a master circuit in an electronic device is communicatively coupled to a data bus that includes a primary data line and a plurality of secondary data lines preconfigured to identify a plurality of processors in the electronic device, respectively. The master circuit detects a processor wake-up trigger(s) asserted on a secondary data line(s) and wakes up a target processor(s) identified by the secondary data line(s). In another aspect, a client circuit(s) identifies the secondary data line(s) preconfigured to identify the target processor(s) and asserts the processor wake-up trigger(s) on the secondary data line(s). By conveying the processor wake-up trigger(s) over the secondary data line(s) preconfigured to identify the target processor(s), it may be possible to optimize processor wake-up efficiency and responsiveness in the master circuit, thus leading to improved power consumption and battery life in the electronic device.

公开(公告)号：US20180173490A1

公开(公告)日：2018-06-21

申请号：US15895965

申请日：2018-02-13

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Amit Gil ,  Oded Schnitzer

IPC: G06F3/16 ,  G10K11/16 ,  G10L19/018

CPC classification number: G06F3/165 ,  G10K11/16 ,  G10L19/012 ,  G10L19/018 ,  H03G3/341 ,  H03G3/348

Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.

公开(公告)号：US20180152779A1

公开(公告)日：2018-05-31

申请号：US15882119

申请日：2018-01-29

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Terrence Brian Remple

IPC: H04R1/10 ,  H04R3/12 ,  H04R3/00 ,  G06F3/16 ,  G06F13/40 ,  H04B1/3827

CPC classification number: H04R1/1033 ,  G06F3/162 ,  G06F13/4045 ,  H04B1/3833 ,  H04R3/005 ,  H04R3/12

Abstract: Low latency transmission systems and methods for long distances in SOUNDWIRE systems are disclosed. In an exemplary aspect, a SOUNDWIRE sub-system is coupled to a long cable through a bridge. The bridge converts SOUNDWIRE signals to signals for transmission over the long cable and converts the signals from the long cable to the SOUNDWIRE signals for transmission in the SOUNDWIRE sub-system. Conversion between signal types may include concatenating signals of a similar type into a group that is serially transmitted over the long cable. Concatenation of bit slots in this manner consumes minimal overhead in bus turnaround, thereby reducing latency. In further aspects, the functionality of the bridge may be incorporated into a headset or a mobile terminal.

公开(公告)号：US20180032307A1

公开(公告)日：2018-02-01

申请号：US15725813

申请日：2017-10-05

Applicant: QUALCOMM Incorporated

Inventor： Alexander Khazin ,  Lior Amarilio

IPC: G06F3/16 ,  G11B27/30 ,  H04R3/00 ,  G06F1/32 ,  G06F1/08

CPC classification number: G06F3/165 ,  G06F1/08 ,  G06F1/324 ,  G11B27/3036 ,  H04R3/00 ,  H04R2460/03 ,  Y02D10/126

Abstract: Power reduction through clock management techniques are disclosed. In one aspect, the clock management is applied to a clock signal on a SOUNDWIRE™ communication bus. In particular, a control system associated with a master device on the communication bus may evaluate frequency requirements of audio streams on the communication bus and select a lowest possible clock frequency that meets the frequency requirements. Lower clock frequencies result in fewer clock transitions and result in a net power saving relative to higher clock frequencies. In the event of a clock frequency change, the master device communicates the clock frequency that will be used prospectively to slave devices on the communication bus, and all devices transition to the new frequency at the same frame boundary. In addition to the power savings, exemplary aspects of the present disclosure do not impact an active audio stream.

公开(公告)号：US09699659B2

公开(公告)日：2017-07-04

申请号：US14803461

申请日：2015-07-20

Applicant: QUALCOMM Incorporated

Inventor： Doron Zehavi ,  Lior Amarilio ,  Zeev Shusterman

IPC: G06F7/04 ,  H04W12/08 ,  G06F9/44 ,  H04W48/04 ,  H04W12/06 ,  H04W4/00 ,  H04L29/08 ,  H04W8/00

CPC classification number: H04W12/08 ,  G06F9/4411 ,  H04L67/12 ,  H04W4/70 ,  H04W8/005 ,  H04W12/06 ,  H04W48/04 ,  H04W48/08

Abstract: In an embodiment, a control device that is configured to onboard a target device to a secure local network by discovering a set of devices over a bootstrapping interface, establishing a bootstrap connection to at least one device from the set of devices in response to the discovery without authorizing the at least one device to access the secure local network, instructing the at least one device via the bootstrap connection to activate an observable function that is configured to be observable to one or more observation entities that are separate from the control device and are in proximity to the at least one device, determining whether an operator of the control device verifies that the observable function has been successfully detected as performed by the target device and selectively authorizing the at least one device to access the secure local network based on the determination.

公开(公告)号：US20160320823A1

公开(公告)日：2016-11-03

申请号：US14702175

申请日：2015-05-01

Applicant: QUALCOMM Incorporated

Inventor： Nir Gerber ,  Lior Amarilio ,  Amit Gil

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3253 ,  G06F13/385 ,  G06F2213/0042 ,  Y02D10/151 ,  Y02D50/20

Abstract: Aspects disclosed in the detailed description include scheduled universal serial bus (USB) low-power operations. In this regard, in one aspect, a USB host controller determines a low-power operation schedule for a USB client device. The low-power operation schedule comprises one or more scheduled low-power operation periods, each corresponding to a respective entry time and a respective exit time. The USB host controller communicates the low-power operation schedule to the USB client device using one or more USB standard packets. By scheduling the one or more scheduled low-power operation periods with respective entry and exit times, the USB host controller or the USB client controller is able to start and end the one or more scheduled low-power operation periods without incurring additional signaling, thus improving efficiency of the USB low-power operation. Further, by communicating the low-power operation schedule using USB standard packets, it is possible to preserve compatibility with USB standards.

Abstract translation: 在详细描述中公开的方面包括调度的通用串行总线（USB）低功率操作。 在这方面，在一方面，USB主机控制器确定USB客户端设备的低功率操作调度。 低功率操作调度包括一个或多个调度的低功率操作周期，每个周期对应于相应的进入时间和相应的退出时间。 USB主机控制器使用一个或多个USB标准数据包将低功耗操作计划传送到USB客户端设备。 通过调度具有相应进入和退出时间的一个或多个调度的低功率操作时段，USB主机控制器或USB客户端控制器能够开始和结束一个或多个调度的低功率操作时段，而不会产生额外的信号，因此 提高USB低功耗操作的效率。 此外，通过使用USB标准分组传送低功率运行调度表，可以保持与USB标准的兼容性。

公开(公告)号：US20160306382A1

公开(公告)日：2016-10-20

申请号：US14713058

申请日：2015-05-15

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Meysam Azin ,  Alexander Khazin ,  Le Wang

IPC: G06F1/10 ,  G06F1/06

CPC classification number: G06F1/10 ,  G06F1/06 ,  G06F13/4291

Abstract: Control circuits for generating output enable signals are disclosed. In one aspect, a control circuit is provided that employs combinatorial logic to generate an output enable signal that meets timing constraints using a standard clock signal, a feedback clock signal based on the standard clock signal, and a single data rate (SDR) data output stream. The control circuit includes a double data rate (DDR) conversion circuit configured to generate a DDR output stream based on a received SDR output stream. The control circuit includes an output enable circuit configured to receive the standard clock signal, feedback clock signal, and DDR output stream, and to generate the output enable signal that is asserted and de-asserted according to the defined timing constraints. The control circuit is configured to generate an accurately timed output enable signal without the need for a fast clock signal in addition to the standard clock signal.

Abstract translation: 公开了用于产生输出使能信号的控制电路。 在一个方面，提供了一种控制电路，其采用组合逻辑来产生使用标准时钟信号满足定时约束的输出使能信号，基于标准时钟信号的反馈时钟信号和单个数据速率（SDR）数据输出 流。 控制电路包括双数据速率（DDR）转换电路，配置为基于接收到的SDR输出流生成DDR输出流。 控制电路包括输出使能电路，其被配置为接收标准时钟信号，反馈时钟信号和DDR输出流，并且根据定义的时序约束生成被断言和解除断言的输出使能信号。 控制电路被配置为产生精确定时的输出使能信号，而不需要除了标准时钟信号之外的快速时钟信号。

公开(公告)号：US20160142454A1

公开(公告)日：2016-05-19

申请号：US14541557

申请日：2014-11-14

Applicant: QUALCOMM Incorporated

Inventor： Magesh Hariharan ,  Lior Amarilio ,  Julio Arceo ,  Aris Balatsos ,  Hans Georg Gruber

IPC: H04L29/06 ,  H04R3/12

CPC classification number: H04L65/4069 ,  G06F3/162 ,  G06F3/165 ,  G06F13/4291 ,  H04L65/604 ,  H04R3/12 ,  H04R5/04 ,  H04R2420/09 ,  H04R2499/11

Abstract: Multi-channel audio alignment schemes are disclosed. One aspect of the present disclosure provides for accumulation of audio samples across multiple related audio channels at an audio source. Related audio channels indicate their interrelatedness, and when all the related audio channels have data to transmit, the source releases the data onto the time slots of the Serial Low-power Inter-chip Media Bus (SLIMbus), such that the related audio channels are within a given segment window of the time slot. This accumulation is repeated at the boundary of every segment window. Similarly, accumulation may be performed at the audio sink. Components within the audio sink may only read received data if status signals from all related sinks indicate that predefined thresholds have been reached. By providing such accumulation options, audio fidelity is maintained across multiple audio data channels.

Abstract translation: 公开了多声道音频对准方案。 本公开的一个方面提供了音频源在多个相关音频通道上的累积。 相关的音频通道表示它们的相互关联性，当所有相关的音频通道都具有要发送的数据时，源将数据释放到串行低功率芯片间媒体总线（SLIMbus）的时隙上，使得相关的音频通道 在时隙的给定分段窗口内。 在每个分段窗口的边界处重复该累积。 类似地，可以在音频接收器处执行累加。 音频接收器内的组件只能从所有相关接收器的状态信号指示已达到预定义的阈值时才读取接收到的数据。 通过提供这种累积选项，可以在多个音频数据通道之间保持音频保真度。