公开(公告)号：US20210050371A1

公开(公告)日：2021-02-18

申请号：US16541289

申请日：2019-08-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Seung-Yeul YANG ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L27/11597 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11592

Abstract: A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a respective transition metal nitride liner and a respective conductive fill material layer, a vertical semiconductor channel vertically extending through the alternating stack, a vertical stack of transition metal nitride spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and discrete ferroelectric material portions laterally surrounding the respective transition metal nitride spacers and located at the levels of the electrically conductive layers.

公开(公告)号：US20190287916A1

公开(公告)日：2019-09-19

申请号：US16020008

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR ,  Tatsuya HINOUE ,  Tomoyuki OBU ,  Tomohiro UNO ,  Yusuke MUKAE

IPC: H01L23/532 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768 ,  H01L29/49

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.

公开(公告)号：US20170373079A1

公开(公告)日：2017-12-28

申请号：US15483862

申请日：2017-04-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Fumitaka AMANO ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Keerti SHUKLA

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L21/768 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11556 ,  H01L21/28282 ,  H01L21/76847 ,  H01L23/53266 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. A barrier layer stack including a crystalline electrically conductive barrier layer and an amorphous barrier layer is formed in the backside recesses prior to formation of a metal fill material layer.

公开(公告)号：US20240290622A1

公开(公告)日：2024-08-29

申请号：US18359664

申请日：2023-07-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan Jayakhar TIRUKKONDA ,  Rahul SHARANGPANI ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA

IPC: H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L21/30608 ,  H01L21/76876 ,  H01L23/5226 ,  H01L23/5283 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method includes forming an alternating stack of first material layers and second material layers over a substrate, forming an etch mask material layer over the alternating stack, loading the etch mask material layer, the alternating stack, and the substrate into an integrated processing apparatus including a plurality of etch chambers and at least one cladding liner deposition chamber; and iteratively performing multiple instances of a unit processing sequence without breaking vacuum. The unit processing sequence includes a respective cladding liner deposition process in which a respective cladding material is anisotropically deposited over the etch mask material layer in a respective one of the at least one cladding liner deposition chamber, and a respective anisotropic etch process in which respective portions of the alternating stack that are not masked by the etch mask material layer are anisotropically etched in a respective etch chamber selected from the plurality of etch chambers.

公开(公告)号：US20240237355A9

公开(公告)日：2024-07-11

申请号：US18350524

申请日：2023-07-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bing ZHOU ,  Monica TITUS ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Senaka KANAKAMEDALA

IPC: H10B43/35 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.

公开(公告)号：US20240138151A1

公开(公告)日：2024-04-25

申请号：US18350524

申请日：2023-07-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bing ZHOU ,  Monica TITUS ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Senaka KANAKAMEDALA

IPC: H10B43/35 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.

公开(公告)号：US20240121960A1

公开(公告)日：2024-04-11

申请号：US18348702

申请日：2023-07-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Rahul SHARANGPANI ,  Kartik SONDHI

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack and having a lateral undulation in a vertical cross-sectional profile such that the memory opening laterally protrudes outward at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and including a vertical stack of blocking dielectric material portions located at the levels of the electrically conductive layers, a vertical stack of discrete memory elements located at the levels of the electrically conductive layers and including a respective contoured charge storage material portion, a tunneling dielectric layer overlying the contoured inner sidewalls of the tubular charge storage material portion, and a vertical semiconductor channel.

公开(公告)号：US20240064991A1

公开(公告)日：2024-02-22

申请号：US17820997

申请日：2022-08-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kartik SONDHI ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Tiffany SANTOS ,  Fei ZHOU ,  Joyeeta NAG ,  Bhagwati PRASAD ,  Adarsh RAJASHEKHAR

IPC: H01L27/11597 ,  H01L27/1159

CPC classification number: H01L27/11597 ,  H01L27/1159

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

公开(公告)号：US20230420370A1

公开(公告)日：2023-12-28

申请号：US17808333

申请日：2022-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Kartik SONDHI

IPC: H01L23/532 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/53266 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements. Each of the electrically conductive layers include a molybdenum layer and a plurality of conductive capping material portions in contact with an outer sidewall of a respective one of the memory opening fill structures.

公开(公告)号：US20230345719A1

公开(公告)日：2023-10-26

申请号：US17659902

申请日：2022-04-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kartik SONDHI ,  Adarsh RAJASHEKHAR ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: An alternating stack of insulating layers and electrically conductive layers is formed over a substrate, and a memory opening vertically extends through the alternating stack. The memory opening is laterally expanded at levels of the insulating layers. At least one blocking dielectric layer is formed in the memory opening. A first vertical stack of discrete charge storage elements is formed at levels of the electrically conductive layers. A second vertical stack of discrete dielectric material portions is formed at the levels of the insulating layers. A tunneling dielectric layer is formed over the first vertical stack and the second vertical stack. A vertical semiconductor channel is formed on the tunneling dielectric layer.