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公开(公告)号:US20210118734A1
公开(公告)日:2021-04-22
申请号:US16948709
申请日:2020-09-29
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: JeongPyo HONG , Mohd Akbar MD SUM , Gordon M. GRIVNA
IPC: H01L21/78 , H01L23/00 , H01L21/3065 , H01L21/67
Abstract: Described implementations include a contaminant-free plasma singulation process, in which residues of materials used during plasma singulation are fully removed from sidewalls of a resulting semiconductor die, without damaging the semiconductor die. From such a contaminant-free plasma singulation process, a semiconductor die may be manufactured. The semiconductor die may include a first plurality of sidewall recesses formed in a sidewall of a substrate of the semiconductor die between a first surface and a second surface of the substrate, each having at most a first depth, as well as a second plurality of sidewall recesses formed in the sidewall of the substrate and disposed between the first plurality of sidewall recesses and the second surface, each having at least a second depth that is greater than the first depth.
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52.
公开(公告)号:US20200321291A1
公开(公告)日:2020-10-08
申请号:US16907520
申请日:2020-06-22
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Gordon M. GRIVNA
IPC: H01L23/58 , H01L21/78 , H01L21/683
Abstract: A semiconductor substrate contains a plurality of openings extending partially into a surface of the semiconductor substrate. A conductive layer is formed with a first portion of the conductive layer over a remaining portion of the surface of the semiconductor substrate between the openings and a second portion of the conductive layer in the openings. The remaining portion of the surface of the semiconductor substrate is removed to lift-off the first portion of the conductive layer while leaving the second portion of the conductive layer in the openings. The semiconductor substrate is singulated to separate the semiconductor die leaving the second portion of the conductive layer over a surface of the semiconductor die. Alternatively, a plurality of openings is formed over each semiconductor die. A conductive layer is formed over a remaining portion of the surface of the semiconductor substrate between the openings and into the openings.
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53.
公开(公告)号:US20200118878A1
公开(公告)日:2020-04-16
申请号:US16715019
申请日:2019-12-16
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Gordon M. GRIVNA
IPC: H01L21/78 , H01L23/544 , H01L21/67 , B28D5/00 , H01L21/3065 , H01L21/477 , H01L21/683
Abstract: A method for forming an electronic device includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces. A layer of material is disposed atop a major surface of the wafer and the layer of material is placed adjacent to first carrier substrate comprising a first adhesive layer. The wafer is singulated through the spaces to form singulation lines. A second carrier substrate comprising a second adhesive layer is placed onto an opposite major surface of the wafer. The method includes moving a mechanical device adjacent to and in a direction generally parallel to one of the first carrier substrate or the second carrier substrate to separate the layer of material in the singulation lines. In one example, the second adhesive layer has an adhesive strength that is less than that of the first adhesive layer.
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公开(公告)号:US20190035687A1
公开(公告)日:2019-01-31
申请号:US16144750
申请日:2018-09-27
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Gordon M. GRIVNA , Stephen ST. GERMAIN
IPC: H01L21/78 , H01L23/495 , H01L29/20 , H01L21/48 , H01L21/02
Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.
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公开(公告)号:US20180158734A1
公开(公告)日:2018-06-07
申请号:US15874307
申请日:2018-01-18
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Gordon M. GRIVNA
IPC: H01L21/78 , H01L21/67 , H01L21/683 , H01L21/3065
CPC classification number: H01L21/78 , H01L21/3065 , H01L21/67069 , H01L21/67092 , H01L21/67132 , H01L21/6836 , H01L2221/68336 , H01L2221/68381
Abstract: A method of singulating a wafer includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces, wherein the wafer has first and second opposing major surfaces, and wherein a layer of material is formed along the second major surface. The method includes placing the wafer onto a carrier substrate. The method includes singulating the wafer through the spaces to form singulation lines after the placing the wafer on the carrier substrate, wherein singulating comprises stopping in proximity to the layer of material. The method includes applying a pressure to the entire wafer thereby separating the layer of material in the singulation lines, wherein applying the pressure comprises using a fluid. The method provide a way to batch separate layers of material disposed on wafers after singulating the wafers.
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56.
公开(公告)号:US20180019259A1
公开(公告)日:2018-01-18
申请号:US15644613
申请日:2017-07-07
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Jefferson W. HALL , Gordon M. GRIVNA
IPC: H01L27/12 , H01L29/66 , H01L29/40 , H01L29/06 , H01L23/528 , H01L21/84 , H01L21/768 , H01L29/78 , H01L21/762
CPC classification number: H01L27/1203 , H01L21/76275 , H01L21/76283 , H01L21/76895 , H01L21/84 , H01L23/528 , H01L29/0649 , H01L29/407 , H01L29/66712 , H01L29/7811 , H01L29/7813
Abstract: A monolithic semiconductor device has a substrate with a power region and control region. The substrate can be a silicon-on-insulator substrate. An opening is formed in the power region and extends partially through the substrate. A semiconductor material is formed within the opening. A power semiconductor device, such as a vertical power transistor, is formed within the semiconductor material. A control logic circuit is formed in the control region. A first isolation trench is formed in the power region to isolate the power semiconductor device and control logic circuit. A second isolation trench is formed in the control region to isolate a first control logic circuit from a second control logic circuit. An interconnect structure is formed over the power region and control region to provide electrical interconnect between the control logic circuit and power semiconductor device. A termination trench is formed in the power region.
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公开(公告)号:US20170004965A1
公开(公告)日:2017-01-05
申请号:US15267488
申请日:2016-09-16
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: William F. BURGHOUT , Dennis Lee CONNER , Michael J. SEDDON , Jay A. YODER , Gordon M. GRIVNA
IPC: H01L21/02 , H01L21/78 , H01L21/683 , H01L23/544
CPC classification number: H01L21/02076 , H01L21/3043 , H01L21/3046 , H01L21/3065 , H01L21/67028 , H01L21/6836 , H01L21/78 , H01L21/7813 , H01L23/544 , H01L2221/68327 , H01L2223/5446
Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a layer of material by placing the semiconductor wafer onto a carrier tape with the layer of material adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the layer of material within the singulation lines, and separating portions of the layer of material using a fluid.
Abstract translation: 在一个实施例中,半导体管芯由具有一层材料的半导体晶片分离,通过将半导体晶片放置在载体带上,该材料层与载体带相邻,形成穿过半导体晶片的分隔线,以暴露出第 分割线,以及使用流体分离材料层的部分。
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公开(公告)号:US20160372323A1
公开(公告)日:2016-12-22
申请号:US15255503
申请日:2016-09-02
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Jason Michael DOUB , Gordon M. GRIVNA
IPC: H01L21/02 , H01L21/683 , H01L21/3065 , H01L21/78 , H01L23/544
CPC classification number: H01L21/02076 , H01L21/02334 , H01L21/3065 , H01L21/32131 , H01L21/67092 , H01L21/67132 , H01L21/6715 , H01L21/6836 , H01L21/78 , H01L23/544 , H01L2221/68327 , H01L2221/68336 , H01L2221/6834 , H01L2221/68381 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer by placing the semiconductor wafer onto a carrier tape, forming singulation lines through the semiconductor wafer, and reducing the presence of residual contaminates on the semiconductor wafer.
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59.
公开(公告)号:US20160172234A1
公开(公告)日:2016-06-16
申请号:US15047874
申请日:2016-02-19
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor: Gordon M. GRIVNA , Zia HOSSAIN , Ali SALIH
IPC: H01L21/762 , H01L29/06 , H01L21/768
CPC classification number: H01L21/76205 , H01L21/76816 , H01L29/0615 , H01L29/0649 , H01L29/407 , H01L29/66734 , H01L29/7811 , H01L29/7813
Abstract: In an embodiment, a method of forming a semiconductor may include forming a plurality of active trenches and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches. The method may also include forming at least one active trench of the plurality of active trenches having corners linking trench ends to sides of active trenches wherein each active trench of the plurality of active trenches has a first profile along the first length and a second profile at or near the trench ends; and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches and having a second profile wherein one of the first profile or the second profile includes a non-linear shape.
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公开(公告)号:US20160064325A1
公开(公告)日:2016-03-03
申请号:US14939873
申请日:2015-11-12
Applicant: Semiconductor Components Industries, LLC
Inventor: Ali SALIH , Chun-Li LIU , Gordon M. GRIVNA
IPC: H01L23/522 , H01L23/532 , H01L29/778
CPC classification number: H01L23/5226 , H01L21/6836 , H01L21/76898 , H01L21/78 , H01L23/4824 , H01L23/49827 , H01L23/53228 , H01L23/53242 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/84 , H01L29/2003 , H01L29/66462 , H01L29/778 , H01L29/7787 , H01L2221/68327 , H01L2224/0345 , H01L2224/0346 , H01L2224/0347 , H01L2224/04034 , H01L2224/05111 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05639 , H01L2224/05647 , H01L2224/06181 , H01L2224/37012 , H01L2224/37013 , H01L2224/37124 , H01L2224/37147 , H01L2224/3716 , H01L2224/37187 , H01L2224/3719 , H01L2224/37639 , H01L2224/37644 , H01L2224/37647 , H01L2224/37655 , H01L2224/37664 , H01L2224/40499 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/84815 , H01L2224/8485 , H01L2924/00014 , H01L2924/12032 , H01L2924/12042 , H01L2924/1305 , H01L2924/13063 , H01L2924/13064 , H01L2924/13091 , H01L2924/00 , H01L2924/01028 , H01L2924/014 , H01L2924/0105 , H01L2924/01047 , H01L2924/01082 , H01L2924/00012 , H01L2924/01029 , H01L2924/07811 , H01L2224/45099
Abstract: In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.
Abstract translation: 在一个实施例中,形成HEMT器件的方法可以包括将导体或多个导体电镀到覆盖在HEMT器件的多个载流电极上的绝缘体上。 该方法还可以包括将连接器附接到导体上或者将多个连接器附接到多个导体上。
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