中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

58 records (took 0.016 seconds)

    Sense amplifier for non-volatile memory devices and related methods
    51.
    发明授权
    Sense amplifier for non-volatile memory devices and related methods 有权

    公开(公告)号：US10068643B2

    公开(公告)日：2018-09-04

    申请号：US15422290

    申请日：2017-02-01

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

    Inventor： Marco Pasotti ,  Marcella Carissimi ,  Rajat Kulshrestha ,  Chantal Auricchio

    IPC: G11C13/00 ,  G11C7/08 ,  G11C7/06

    Abstract: A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and complementary PCM cells, and a sense amplifier is coupled to the column decoder. The sense amplifier includes a current integrator configured to receive first and second currents of a given PCM cell and complementary PCM cell, respectively. A current-to-voltage converter is coupled to the current integrator and is configured to receive the first and second currents, and to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively. A logic circuit is coupled to the first and second nodes and is configured to disable the column decoder and to discharge the bitline and complementary bitline voltages in response to the first and second voltages.

    Memory device including decoder for a program pulse and related methods
    52.
    发明授权
    Memory device including decoder for a program pulse and related methods 有权

    公开(公告)号：US10049736B2

    公开(公告)日：2018-08-14

    申请号：US15433795

    申请日：2017-02-15

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

    Inventor： Marco Pasotti ,  Marcella Carissimi ,  Vikas Rana

    IPC: G11C11/00 ,  G11C13/00

    Abstract: An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes a first decoder circuit having a respective plurality of transistors having a first conductivity type being coupled together and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM cell. In addition, the integrated circuit includes a second decoder circuit having a plurality of transistors having a second conductivity type being coupled together and to the given bitline and configured to discharge the given bitline at an end of the program current pulse.

    Voltage doubling circuit and charge pump applications for the voltage doubling circuit
    53.
    发明授权
    Voltage doubling circuit and charge pump applications for the voltage doubling circuit 有权

    公开(公告)号：US09634562B1

    公开(公告)日：2017-04-25

    申请号：US15177830

    申请日：2016-06-09

    Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

    Inventor： Vikas Rana ,  Marco Pasotti ,  Fabio De Santis

    IPC: G05F1/10 ,  G05F3/02 ,  H02M3/07

    CPC classification number: H02M3/073

    Abstract: A voltage doubler circuit supports operation in a positive voltage boosting mode to positively boost voltage from a first node to a second node and operation in a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuits receive two clock signals having different high voltage levels. A series of voltage doubler circuit are connected in a charge pump with controllable operation in the first and second modes. A connecting circuit interconnects the first and second nodes of the voltage doubler circuits to provide a first connection path, with a first input voltage, to support the positive voltage boosting mode operation and a second connection path, with a proper input voltage, to support the negative voltage boosting mode. A discharge circuit is provided to discharge the voltage doubler circuits when operation of the charge pump circuit is terminated.

    Non volatile memory cell and memory array
    54.
    发明授权
    Non volatile memory cell and memory array 有权

    公开(公告)号：US09627066B1

    公开(公告)日：2017-04-18

    申请号：US15210709

    申请日：2016-07-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marco Pasotti ,  Fabio de Santis ,  Roberto Bregoli ,  Dario Livornesi

    IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/14

    CPC classification number: G11C16/0441 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

    Abstract: A non-volatile memory cell for storing a single bit is disclosed. The non-volatile memory cell includes an access transistor including a gate, a first body, a first source/drain node, and a second source/drain node. The non-volatile memory cell also includes a first floating gate storage transistor that has a third source/drain node, a second body, a fourth source/drain node, and a first floating gate including a first storage node. The third source/drain node is coupled to the second source/drain node. The non-volatile memory cell further includes a first capacitor, a second capacitor, and a second floating gate storage transistor. The first capacitor has a first plate coupled to the first storage node and an opposite second plate. The second floating gate storage transistor includes a fifth source/drain node, a third body, a sixth source/drain node, a second floating gate including a second storage node. The fifth source/drain node is coupled to the fourth source/drain node. The second capacitor includes a third plate coupled to the second storage node and having an opposite fourth plate. The second plate is coupled to the fourth plate, and the first body of the access transistor is coupled to the second body and the third body.

    Identification of a condition of a sector of memory cells in a non-volatile memory
    56.
    发明授权
    Identification of a condition of a sector of memory cells in a non-volatile memory 有权
    识别非易失性存储器中的存储器单元的扇区的状况

    公开(公告)号：US09443566B2

    公开(公告)日：2016-09-13

    申请号：US14061977

    申请日：2013-10-24

    Applicant: STMicroelectronics S.R.L.

    Inventor： Marcella Carissimi ,  Marco Pasotti ,  Fabio De Santis

    IPC: G11C16/28 ,  G11C7/06 ,  G11C7/08 ,  G11C16/04

    CPC classification number: G11C7/22 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/10 ,  G11C16/0441 ,  G11C16/28

    Abstract: An embodiment solution for operating a non-volatile memory of a complementary type is proposed. The non-volatile memory includes a plurality of sectors of memory cells, each memory cell being adapted to take a programmed state or an erased state. Moreover, the memory cells are arranged in locations each formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. In an embodiment, a corresponding method includes the following steps: selecting at least one of the sectors, determining an indication of the number of memory cells in the programmed state and an indication of the number of memory cells in the erased state of the selected sector, and identifying the condition of the selected sector according to a comparison between the indication of the number of memory cells in the programmed state and the indication of the number of memory cells in the erased state.

    Abstract translation: 提出了用于操作互补型非易失性存储器的实施例解决方案。 非易失性存储器包括存储器单元的多个扇区，每个存储器单元适于采取编程状态或擦除状态。 此外，存储单元被布置在由直接存储单元和互补存储单元形成的位置中。 当相应的存储器单元处于相同的状态并且处于写入状态时，非易失性存储器的每个扇区处于非写入状态，其中当其中的每个位置存储第一逻辑值或第二逻辑值时， 位置分别处于不同状态的第一组合或处于不同状态的第二组合中。 在一个实施例中，相应的方法包括以下步骤：选择扇区中的至少一个，确定编程状态下的存储器单元的数量的指示以及所选扇区的擦除状态中的存储器单元的数量的指示 并且根据编程状态下的存储单元的数量的指示与擦除状态下的存储单元的数量的指示之间的比较来识别所选扇区的状况。

Patent Agency Ranking