Poly-crystalline silicon film ladder resistor
    51.
    发明授权
    Poly-crystalline silicon film ladder resistor 失效
    多晶硅膜梯形电阻

    公开(公告)号:US6013940A

    公开(公告)日:2000-01-11

    申请号:US516627

    申请日:1995-08-18

    摘要: A resistor ladder network may be formed with a reduced space on a semiconductor substrate by patterning a plurality of layers of resistive polycrystalline silicon films spaced by insulating layers. Such a device includes a first insulating film formed on a semiconductor substrate, one or more serial-connected first resistors formed in a first polycrystalline silicon film provided on the semiconductor substrate via the first insulating film, a second insulating film provided on the first polycrystalline silicon film, one or more series-connected second resistors formed in a second polycrystalline silicon film provided apart from the first polycrystalline silicon film via the second insulating film, the second polycrystalline silicon film being connected to the first polycrystalline silicon film. A third insulating film is provided over the second polycrystalline silicon film, and metal wires provided on a surface of the second polycrystalline silicon film via contact holes formed in the third insulating film. Preferably, the first polycrystalline silicon film is thicker than the second polycrystalline silicon film, the impurity concentration of the first polycrystalline silicon film is lower than the impurity concentration of the second polycrystalline silicon film, and the grain size of the first polycrystalline silicon film is smaller than that of the second polycrystalline silicon film.

    摘要翻译: 可以通过对由绝缘层隔开的多层电阻多晶硅膜进行构图而在半导体衬底上形成具有减小的空间的电阻梯形网络。 这种器件包括形成在半导体衬底上的第一绝缘膜,经由第一绝缘膜形成在设置在半导体衬底上的第一多晶硅膜中的一个或多个串联连接的第一电阻器,设置在第一多晶硅上的第二绝缘膜 膜,一个或多个串联连接的第二电阻器,形成在通过第二绝缘膜与第一多晶硅膜分开设置的第二多晶硅膜中,第二多晶硅膜连接到第一多晶硅膜。 在第二多晶硅膜上设置第三绝缘膜,通过形成在第三绝缘膜中的接触孔,设置在第二多晶硅膜的表面上的金属线。 优选地,第一多晶硅膜比第二多晶硅膜厚,第一多晶硅膜的杂质浓度低于第二多晶硅膜的杂质浓度,第一多晶硅膜的晶粒尺寸较小 比第二多晶硅膜的厚度大。

    Method of producing a semiconductor device for a light valve
    55.
    发明授权
    Method of producing a semiconductor device for a light valve 失效
    制造光阀半导体装置的方法

    公开(公告)号:US5633176A

    公开(公告)日:1997-05-27

    申请号:US463687

    申请日:1995-06-05

    摘要: A semiconductor substrate is utilized to integrally form a drive circuit and a pixel array to produce a transparent semiconductor device for a light valve comprising a pixel array region and a drive circuit region on a major face of the semiconductor substrate. A stopper film is formed on the major face of the semiconductor substrate at the pixel array region, and a pixel array is formed over the silicon oxide stopper film. A drive circuit is formed on the drive circuit region, and silicon oxide posts are embedded in the major face of the semiconductor substrate at the drive circuit region. A thickness of the semiconductor substrate is then selectively removed from a back face opposite to the major face thereof to reach the stopper film. After the selective removing step, the portion of the semiconductor substrate under the pixel region is completely removed while a portion of the semiconductor substrate under the drive circuit region remains.

    摘要翻译: 半导体衬底被用于整体形成驱动电路和像素阵列以产生用于光阀的透明半导体器件,其包括在半导体衬底的主面上的像素阵列区域和驱动电路区域。 在像素阵列区域的半导体基板的主面上形成有阻挡膜,在氧化硅阻挡膜上形成像素阵列。 在驱动电路区域上形成驱动电路,在驱动电路区域,氧化硅柱嵌入半导体基板的主面。 然后从与其主面相反的背面选择性地去除半导体衬底的厚度以到达阻挡膜。 在选择性去除步骤之后,半导体衬底在像素区域下方的部分被完全去除,而驱动电路区域下的半导体衬底的一部分保留。

    Semiconductor integrated circuit
    56.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号:US5610428A

    公开(公告)日:1997-03-11

    申请号:US476221

    申请日:1995-06-07

    CPC分类号: H01L29/7883 H01L27/105

    摘要: A semiconductor integrated circuit comprises a semiconductor substrate of a first conductivity type, at least one electrically erasable floating gate type semiconductor non-volatile memory transistor disposed on a surface of the semiconductor substrate, a well region of a second conductivity type formed in the surface of the semiconductor substrate, and a program voltage switching transistor of the first conductivity type disposed in the well region. A field insulation film is disposed on the surface of the semiconductor substrate. A field dope region of the first conductivity type is provided beneath the field insulation film. The field dope region preferably has an impurity concentration higher than an impurity concentration of the semiconductor substrate. By this construction, current leakage is prevented at the time when a high voltage occurs such as, for example, when performing a writing operation with respect to EEPROM.

    摘要翻译: 半导体集成电路包括第一导电类型的半导体衬底,设置在半导体衬底的表面上的至少一个电可擦除浮栅型半导体非易失性存储晶体管,形成在第二导电类型的表面上的第二导电类型的阱区 所述半导体衬底以及设置在所述阱区中的所述第一导电类型的编程电压开关晶体管。 在半导体衬底的表面上设置场绝缘膜。 第一导电类型的场掺杂区域设置在场绝缘膜的下方。 场掺杂区优选具有高于半导体衬底的杂质浓度的杂质浓度。 通过这种结构,在诸如例如当对EEPROM执行写入操作时出现高电压时,防止了电流泄漏。

    Semiconductor device with monosilicon layer
    57.
    发明授权
    Semiconductor device with monosilicon layer 失效
    具有单晶硅层的半导体器件

    公开(公告)号:US5574292A

    公开(公告)日:1996-11-12

    申请号:US57986

    申请日:1993-05-05

    摘要: A semiconductor device has an integrated circuit formed in a monosilicon layer provided on an electrically insulative material. The monosilicon layer has an integrated circuit formed thereon, and a passivation film covers the integrated circuit. A support member is fixed to the electrically insulative material through an adhesive layer to support the monosilicon layer. The integrated circuit comprises an MIS transistor having a source region, drain region, and channel region formed in the monosilicon layer. The semiconductor device is suitable for use in a high speed, high capacity liquid crystal light valve having a structure where a pixel switching element group and a peripheral driver circuit are formed integrally on a common substrate.

    摘要翻译: 半导体器件具有形成在设置在电绝缘材料上的单硅层中的集成电路。 单晶硅层具有形成在其上的集成电路,钝化膜覆盖集成电路。 支撑构件通过粘合剂层固定到电绝缘材料以支撑单硅层。 集成电路包括具有形成在单硅层中的源极区,漏极区和沟道区的MIS晶体管。 该半导体装置适用于具有像素开关元件组和周边驱动电路一体地形成在共同的基板上的结构的高速,高容量的液晶光阀。

    Semiconductor nonvolatile memory
    60.
    发明授权
    Semiconductor nonvolatile memory 失效
    半导体非易失性存储器

    公开(公告)号:US5053842A

    公开(公告)日:1991-10-01

    申请号:US530269

    申请日:1990-05-30

    申请人: Yoshikazu Kojima

    发明人: Yoshikazu Kojima

    IPC分类号: H01L27/115 H01L29/788

    CPC分类号: H01L29/7885 H01L27/115

    摘要: The invention is directed to a semiconductor nonvolatile memory of the floating gate type having dual gate structure comprised of a first channel region having a channel resistance controlled by a control gate electrode and a second channel region having a channel resistance controlled by a floating gate electrode. The first channel region is formed on one face section of semiconductor substrate which has a crystal face orientation different from that of another face section on which the second channel region is formed. By such construction, channel length of the first and second channel regions can be shortened to increase memory capacity density and to improve quality.

    摘要翻译: 本发明涉及具有双栅极结构的浮栅型半导体非易失性存储器,由具有由控制栅极电极控制的沟道电阻的第一沟道区和由浮置栅电极控制的沟道电阻的第二沟道区构成。 第一沟道区形成在半导体衬底的一个面部区域上,其具有不同于其上形成有第二沟道区的另一面部区域的晶面取向。 通过这样的结构,可以缩短第一和第二通道区域的通道长度,以增加存储器容量密度并提高质量。