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    Methods for fabricating FinFET semiconductor devices using L-shaped spacers
    52.
    发明授权
    Methods for fabricating FinFET semiconductor devices using L-shaped spacers 有权
    使用L形间隔物制造FinFET半导体器件的方法

    公开(公告)号：US08404592B2

    公开(公告)日：2013-03-26

    申请号：US12509918

    申请日：2009-07-27

    申请人： Scott Luning ,  Frank S. Johnson

    发明人： Scott Luning ,  Frank S. Johnson

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3086 ,  H01L21/845 ,  H01L29/66795

    摘要： Methods for fabricating semiconductor structures, such as fin structures of FinFET transistors, are provided. In one embodiment, a method comprises providing a semiconductor substrate and forming a plurality of mandrels overlying the semiconductor substrate. Each of the mandrels has sidewalls. L-shaped spacers are formed about the sidewalls of the mandrels. Each L-shaped spacer comprises a rectangular portion disposed at a base of a mandrel and an orthogonal portion extending from the rectangular portion. Each L-shaped spacer also has a spacer width. The orthogonal portions are removed from each of the L-shaped spacers leaving at least a portion of the rectangular portions. The semiconductor substrate is etched to form fin structures, each fin structure having a width substantially equal to the spacer width.

    摘要翻译： 提供了制造半导体结构的方法，例如FinFET晶体管的鳍结构。 在一个实施例中，一种方法包括提供半导体衬底并形成覆盖半导体衬底的多个心轴。 每个心轴都有侧壁。 围绕心轴的侧壁形成L形间隔物。 每个L形间隔件包括设置在心轴的基部和从矩形部分延伸的正交部分的矩形部分。 每个L形间隔物也具有间隔物宽度。 从每个L形间隔件中取出正交部分，留下矩形部分的至少一部分。 蚀刻半导体衬底以形成鳍结构，每个鳍结构的宽度基本上等于间隔物宽度。

    SEMICONDUCTOR DEVICE WITH STRESSED FIN SECTIONS
    53.
    发明申请
    SEMICONDUCTOR DEVICE WITH STRESSED FIN SECTIONS 有权
    半导体器件与强化部分

    公开(公告)号：US20110266622A1

    公开(公告)日：2011-11-03

    申请号：US13180300

    申请日：2011-07-11

    申请人： Scott Luning ,  Frank Scott Johnson

    发明人： Scott Luning ,  Frank Scott Johnson

    IPC分类号： H01L29/786

    CPC分类号： H01L29/7842 ,  H01L29/66795 ,  H01L29/785

    摘要： A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

    摘要翻译： 提供一种制造半导体器件的方法。 所述方法在半导体衬底上形成翅片布置，所述翅片布置包括一个或多个半导体翅片结构。 该方法通过形成覆盖鳍片布置的栅极布置继续，其中栅极布置包括一个或多个相邻栅极结构。 该方法通过在每个栅极结构的侧壁周围形成外部间隔来进行。 然后使用栅极结构和外部间隔物作为蚀刻掩模来选择性地蚀刻鳍片布置，从而导致栅极结构下面的一个或多个半导体鳍片部分。 该方法通过在一个或多个半导体鳍片部分的侧壁附近形成应力/应变诱导材料来继续。

    STRESSED FIELD EFFECT TRANSISTOR AND METHODS FOR ITS FABRICATION
    54.
    发明申请
    STRESSED FIELD EFFECT TRANSISTOR AND METHODS FOR ITS FABRICATION 有权
    应力场效应晶体管及其制造方法

    公开(公告)号：US20080079033A1

    公开(公告)日：2008-04-03

    申请号：US11536126

    申请日：2006-09-28

    申请人： Andrew M. Waite ,  Scott Luning

    发明人： Andrew M. Waite ,  Scott Luning

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

    摘要： A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.

    摘要翻译： 提供了一种应力场效应晶体管及其制造方法。 场效应晶体管包括具有覆盖硅衬底的栅极绝缘体的硅衬底。 栅电极覆盖栅极绝缘体，并且在栅电极下面的硅衬底中限定沟道区。 具有第一厚度的第一硅锗区域嵌入在硅衬底中并与沟道区域接触。 具有大于第一厚度并且与沟道区间隔开的第二厚度的第二硅锗区域也嵌入在硅衬底中。

    Method of forming a semiconductor device having an epitaxial layer and device thereof
    56.
    发明申请
    Method of forming a semiconductor device having an epitaxial layer and device thereof 审中-公开
    形成具有外延层的半导体器件的方法及其装置

    公开(公告)号：US20060281271A1

    公开(公告)日：2006-12-14

    申请号：US11150899

    申请日：2005-06-13

    申请人： David Brown ,  William En ,  Thorsten Kammler ,  Paul Besser ,  Scott Luning

    发明人： David Brown ,  William En ,  Thorsten Kammler ,  Paul Besser ,  Scott Luning

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6653 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

    摘要： Integration schemes are presented which provide for decoupling the placement of deep source/drain (S/D) implants with respect to a selective epitaxial growth (SEG) raised S/D region, as well as decoupling silicide placement relative to a raised S/D feature. These integration schemes may be combined in multiple ways to permit independent control of the placement of these features for optimizing device performance. The methodology utilizes multiple spacers to decrease current crowding effects in devices due to proximity effects between LDD and deep S/D regions in reduced architecture devices.

    摘要翻译： 提出了集成方案，其提供了相对于选择性外延生长（SEG）引起的S / D区域去耦合深源/漏（S / D）植入物的放置以及相对于升高的S / D去耦硅化物放置 特征。 这些集成方案可以以多种方式组合，以允许独立控制这些特征的放置以优化装置性能。 该方法利用多个间隔物来减少由于减少的架构设备中LDD与深S / D区域之间的邻近效应而导致的器件中的电流拥挤效应。

    Semiconductor processing employing a semiconductor spacer
    59.
    发明授权
    Semiconductor processing employing a semiconductor spacer 有权
    采用半导体衬垫的半导体处理

    公开(公告)号：US06642134B2

    公开(公告)日：2003-11-04

    申请号：US09401797

    申请日：1999-09-22

    申请人： Emi Ishida ,  Scott Luning

    发明人： Emi Ishida ,  Scott Luning

    IPC分类号： H01L213205

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/823864 ,  H01L29/6656

    摘要： A semiconductor device is provided with semiconducting sidewall spacers used in the formation of source/drain regions. The semiconducting sidewall spacers also reduce the possibility of suicide shorting through shallow source/drain junctions. Embodiments include doping the semiconducting sidewall spacers so that they serve as a source of impurities for forming source/drain extensions during activation annealing.

    摘要翻译： 半导体器件设置有用于形成源极/漏极区域的半导体侧壁间隔物。 半导体侧壁间隔物还减少了通过浅源极/漏极结的自杀性短路的可能性。 实施例包括掺杂半导体侧壁间隔物，使得它们用作在激活退火期间形成源极/漏极延伸的杂质源。

    Low-K sub spacer pocket formation for gate capacitance reduction
    60.
    发明授权
    Low-K sub spacer pocket formation for gate capacitance reduction 有权
    用于栅极电容降低的低K子间隔袋形成

    公开(公告)号：US06351013B1

    公开(公告)日：2002-02-26

    申请号：US09352339

    申请日：1999-07-13

    申请人： Scott Luning ,  David Wu ,  Khanh Tran

    发明人： Scott Luning ,  David Wu ,  Khanh Tran

    IPC分类号： H01L31062

    CPC分类号： H01L29/6659 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/3124 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66598 ,  Y10S257/90

    摘要： The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

    摘要翻译： 通过在源极/漏极区域之上的栅电极的角部形成低介电常数（K）材料的子间隔物来减小半导体器件的栅电极和源/漏区之间的电容。 随后，在子间隔物之上形成绝缘侧壁间隔物以屏蔽浅源/漏区，从而避免随后的杂质注入。 所得到的半导体器件在保持电路可靠性的同时，在栅极电极和源极/漏极区域之间表现出减小的电容。