利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

93 条记录 (耗时 0.036 秒)

    High-density contact holes
    51.
    发明授权
    High-density contact holes 有权
    高密度接触孔

    公开(公告)号：US07704875B1

    公开(公告)日：2010-04-27

    申请号：US12024784

    申请日：2008-02-01

    申请人： Albert Wu ,  Chien-Chuan Wei

    发明人： Albert Wu ,  Chien-Chuan Wei

    IPC分类号： H01L21/475

    CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/31144

    摘要： Methods for patterning high-density contact holes and contacts are described herein. Embodiments of the present invention provide a method comprising depositing a first dummy layer over a substrate to form a first pattern; depositing a second dummy layer over the substrate to form a second pattern, the second pattern overlapping the first pattern at a plurality of locations; etching the first and second dummy layers to form a plurality of posts at the plurality of locations; forming a dielectric layer over the substrate; and etching the posts to form a plurality of contact holes in the dielectric layer. Other embodiments may be described and claimed.

    摘要翻译： 本文描述了用于图案化高密度接触孔和触点的方法。 本发明的实施例提供了一种方法，包括在衬底上沉积第一虚拟层以形成第一图案; 在所述衬底上沉积第二虚拟层以形成第二图案，所述第二图案在所述多个位置处与所述第一图案重叠; 蚀刻第一和第二虚拟层以在多个位置形成多个柱; 在所述衬底上形成介电层; 并且蚀刻所述柱以在所述介电层中形成多个接触孔。 可以描述和要求保护其他实施例。

    Insole cushioning device with repelling magnetic field
    52.
    发明授权
    Insole cushioning device with repelling magnetic field 失效
    鞋垫缓冲装置具有排斥磁场

    公开(公告)号：US07694440B1

    公开(公告)日：2010-04-13

    申请号：US11618901

    申请日：2006-12-31

    申请人： Albert Wu

    发明人： Albert Wu

    IPC分类号： A43B13/38 ,  A43B13/18

    CPC分类号： A43B17/02 ,  A43B1/0054

    摘要： A system is disclosed for an insole for use in an article of footwear. The insole includes a bottom cushion layer; a lower intermediate layer; a middle flexible layer; an upper intermediate layer; and an upper cushion layer. The layers are coupled together by either lamination or gluing. The lower intermediate layer and the upper intermediate layer are respectively embedded with a first array of magnet elements and a second array of magnet elements, such that the first array of magnet elements and the second array of magnet elements generate a repelling magnetic field that results in a repelling mechanical force that pulls the upper intermediate layer away from the lower intermediate layer. This invention is not affected by material fatigue due to prolonged pressure or temperature stress that is common in insoles for use in articles of footwear.

    摘要翻译： 公开了一种用于鞋类物品的鞋垫的系统。 鞋垫包括底垫层; 下中间层; 中间柔性层; 上层中间层; 和上缓冲层。 层通过层压或胶合而连接在一起。 下部中间层和上部中间层分别嵌有磁体元件的第一阵列和第二磁体元件阵列，使得磁体元件的第一阵列和第二磁体元件阵列产生排斥磁场，导致排斥磁场 排斥机械力，其将上中间层拉离下中间层。 由于用于鞋类物品的鞋垫中常见的压力或温度应力的延长，本发明不受材料疲劳的影响。

    Stack die packages
    53.
    发明申请
    Stack die packages 有权
    堆栈包装

    公开(公告)号：US20080006948A1

    公开(公告)日：2008-01-10

    申请号：US11801317

    申请日：2007-05-09

    申请人： Albert Wu ,  Huahung Kao

    发明人： Albert Wu ,  Huahung Kao

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/731 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00012

    摘要： Integrated circuit packages having corresponding methods comprise: a substrate comprising first electric contacts; a first wirebond integrated circuit die mechanically coupled to the substrate and comprising second electric contacts electrically coupled to the first electric contacts of the substrate by first electrically conductive wires; a flip-chip integrated circuit die comprising third electric contacts electrically coupled to the second electric contacts of the first wirebond integrated circuit die by electrically conductive bumps; and a second wirebond integrated circuit die mechanically coupled to the flip-chip integrated circuit die and comprising fourth electric contacts electrically coupled to the second electric contacts of the first wirebond integrated circuit die, or the first electric contacts of the substrate, or both, by second electrically conductive wires.

    摘要翻译： 具有相应方法的集成电路封装包括：基板，包括第一电触头; 机械耦合到所述衬底并且包括通过第一导电线电耦合到所述衬底的所述第一电触点的第二电触点的第一引线键合集成电路模; 一种倒装芯片集成电路芯片，包括通过导电凸块电耦合到第一引线键合集成电路芯片的第二电触头的第三电触头; 以及第二引线键合集成电路芯片，其机械耦合到所述倒装芯片集成电路管芯并且包括电耦合到所述第一引线键合集成电路管芯的所述第二电触头或所述衬底的所述第一电触点或两者的第四电触点， 第二导电线。

    Method of making an EEPROM
    56.
    发明授权
    Method of making an EEPROM 失效
    制造EEPROM的方法

    公开(公告)号：US5453388A

    公开(公告)日：1995-09-26

    申请号：US132941

    申请日：1993-10-07

    申请人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

    发明人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

    IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L21/266 ,  H01L21/8247

    CPC分类号： H01L29/66825 ,  H01L29/7883 ,  H01L27/115

    摘要： Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

    摘要翻译： 公开了使用片上电压倍增器电路仅需要5伏外部源的闪速EEPROM单元，以提供在编程和擦除模式期间实现Fowler-Nordheim隧穿所需的高电压。 浮置栅极和控制栅极之间以及浮置栅极和漏极区域之间的介电层的性质不同，以便于浮动栅极的编程和擦除。 还公开了一种通过在浮动栅极和控制栅极之间形成绝缘层以使电容低于浮置栅极和漏极区域之间的绝缘层的电容的电容来产生快闪EEPROM单元的方法。

    High-density patterning
    57.
    发明授权
    High-density patterning 失效
    高密度图案化

    公开(公告)号：US08609528B1

    公开(公告)日：2013-12-17

    申请号：US13204370

    申请日：2011-08-05

    申请人： Pantas Sutardja ,  Albert Wu ,  Winston Lee ,  Peter Lee ,  Chien-Chuan Wei ,  Runzi Chang

    发明人： Pantas Sutardja ,  Albert Wu ,  Winston Lee ,  Peter Lee ,  Chien-Chuan Wei ,  Runzi Chang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76816

    摘要： Methods for patterning high-density features are described herein. Embodiments of the present invention provide a method comprising patterning a first subset of a pattern, the first subset configured to form a plurality of lines over the substrate, and patterning a second subset of the pattern, the second subset configured to form a plurality of islands over the substrate, wherein said patterning the first subset and said patterning the second subset comprise at least two separate patterning operations.

    摘要翻译： 本文描述了用于图案化高密度特征的方法。 本发明的实施例提供了一种方法，包括对图案的第一子集进行图案化，所述第一子集被配置成在所述衬底上形成多个线，以及图案化所述图案的第二子集，所述第二子集被配置为形成多个岛 其中所述图案化所述第一子集并且所述图案化所述第二子集包括至少两个单独的图案化操作。

    Low base resistance bipolar junction transistor array
    58.
    发明授权
    Low base resistance bipolar junction transistor array 有权
    低基极电阻双极结晶体管阵列

    公开(公告)号：US07863709B1

    公开(公告)日：2011-01-04

    申请号：US12104254

    申请日：2008-04-16

    申请人： Pantas Sutardja ,  Albert Wu ,  Runzi Chang ,  Chien-Chuan Wei ,  Winston Lee ,  Peter Lee

    发明人： Pantas Sutardja ,  Albert Wu ,  Runzi Chang ,  Chien-Chuan Wei ,  Winston Lee ,  Peter Lee

    IPC分类号： H01L27/082

    CPC分类号： H01L27/1026

    摘要： Methods and apparatuses directed to low base resistance bipolar junction transistor (BJT) devices are described herein. A low base resistance BJT device may include a collector layer, a base layer formed on the collector layer, a plurality of isolation trench lines formed in the base layer and extending into the collector layer, and a plurality of polysilicon lines formed on the base layer parallel to and overlapping the plurality of isolation trench lines. The base layer may be N-doped or P-doped.

    摘要翻译： 本文描述了针对低基极电阻双极结型晶体管（BJT）器件的方法和装置。 低电阻BJT器件可以包括集电极层，形成在集电极层上的基极层，形成在基极层中并延伸到集电极层中的多个隔离沟槽线，以及形成在基极层上的多个多晶硅线 平行于并重叠多个隔离沟槽线。 基层可以是N掺杂或P掺杂的。

    Methods of making and using fuse structures, and integrated circuits including the same
    59.
    发明授权
    Methods of making and using fuse structures, and integrated circuits including the same 有权
    制造和使用熔丝结构的方法，以及包括其的集成电路

    公开(公告)号：US07820493B1

    公开(公告)日：2010-10-26

    申请号：US12012724

    申请日：2008-02-04

    申请人： Chuan-Cheng Cheng ,  Shuhua Yu ,  Roawen Chen ,  Albert Wu

    发明人： Chuan-Cheng Cheng ,  Shuhua Yu ,  Roawen Chen ,  Albert Wu

    IPC分类号： H01L27/10 ,  H01L21/8239

    CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

    摘要翻译： 保险丝结构，包括该结构的集成电路，以及使用该保险丝的结构和（重新）配置电路的方法。 熔丝结构通常包括（a）具有至少两个电耦合到其上的电路元件的导电结构，（b）导电结构上的电介质层，和（c）第一介电层和导电结构上的第一透镜， 以至少部分地将光聚焦到导电结构上。 制造该结构的方法通常包括以下步骤：（1）形成电耦合到第一和第二电路元件的导电结构，（2）在其上形成介电层，和（3）在电介质层上或之上形成透镜， 在导电结构之上，透镜被配置为至少部分地将光聚焦到导电结构上。 （重新）配置电路的方法通常包括以下步骤：（i）在电路表面上或附近照射足够的电气断开位于透镜下方的对应的第一保险丝的至少一个透镜，并且禁用电路的第一配置 ，以及（ii）在该电路表面上或其附近照射至少一个其他透镜，足以使位于该透镜下方的对应的第二保险丝电气断开并使电路能够进行第二配置。 该结构和方法有利地提供具有改善的可靠性和更小的芯片面积的熔丝结构，从而提高制造工艺的产量和每个晶片的模具数量（总和良好）。