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    SEMICONDUCTOR DEVICE
    51.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20140175431A1

    公开(公告)日：2014-06-26

    申请号：US14105250

    申请日：2013-12-13

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

    IPC: H01L27/108 ,  H01L29/786

    CPC classification number: H01L27/115 ,  G11C16/0416 ,  H01L21/28518 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/10855 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/24 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

    Abstract translation: 第一晶体管，包括沟道形成区域，第一栅极绝缘层，第一栅极电极和第一源极电极以及第一漏极电极; 第二晶体管，包括氧化物半导体层，第二源极和第二漏极，第二栅极绝缘层和第二栅电极; 并且设置包括第二源电极和第二漏电极之一的电容器，第二栅极绝缘层和设置成与第二栅极绝缘层上的第二源电极和第二漏极之一重叠的电极。 第一栅极电极和第二源极电极和第二漏极电极中的一个彼此电连接。

    SEMICONDUCTOR DEVICE
    52.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20140169100A1

    公开(公告)日：2014-06-19

    申请号：US14186005

    申请日：2014-02-21

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

    IPC: G11C16/10 ,  G11C16/04

    CPC classification number: H01L27/1052 ,  G11C5/06 ,  G11C7/12 ,  G11C11/404 ,  G11C11/405 ,  G11C11/565 ,  G11C16/0408 ,  G11C16/10 ,  G11C2211/4016 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/263 ,  H01L29/7869

    Abstract: Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

    Abstract translation: 公开了用作多值存储器件的半导体器件，包括：串联连接的存储器单元; 选择存储单元并驱动第二信号线和字线的驱动器电路; 选择写入电位的驱动器电路并将其输出到第一信号线; 读取电路，比较位线的电位和参考电位; 以及产生写入电位和参考电位的电位产生电路。 一个存储单元包括：连接到位线的第一晶体管和源极线; 连接到第一和第二信号线的第二晶体管; 以及连接到字线，位线和源极线的第三晶体管。 第二晶体管包括氧化物半导体层。 第一晶体管的栅电极连接到第二晶体管的源极和漏极之一。

    MICROCONTROLLER
    53.
    发明申请
    MICROCONTROLLER 有权
    微控制器

    公开(公告)号：US20140068300A1

    公开(公告)日：2014-03-06

    申请号：US14013082

    申请日：2013-08-29

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tatsuji Nishijima ,  Hidetomo Kobayashi ,  Tomoaki Atsumi ,  Kiyoshi Kato

    IPC: G06F1/32

    CPC classification number: G06F1/3243 ,  G06F1/3287 ,  G11C5/148 ,  G11C11/405 ,  Y02D10/152 ,  Y02D10/171

    Abstract: To provide a microcontroller that can operate in a low power consumption mode. The microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register of the peripheral circuit is formed at an interface with a bus line. A power gate is provided for control of power supply, and the microcontroller can operate in the low power consumption mode where some circuits alone are active, in addition to in a normal operation mode where all circuits are active. A register with no power supply in the low power consumption mode, such as a register of the CPU, includes a volatile memory and a nonvolatile memory.

    Abstract translation: 提供可在低功耗模式下工作的微控制器。 微控制器包括CPU，存储器和诸如定时器电路的外围电路。 外围电路的寄存器形成在与总线线路的接口处。 提供电源门用于控制电源，并且除了在所有电路都处于活动状态的正常操作模式之外，微控制器可以以低功耗模式操作，其中一些电路单独有效。 在诸如CPU的寄存器的低功耗模式中没有电源的寄存器包括易失性存储器和非易失性存储器。

    SEMICONDUCTOR DEVICE
    54.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20130200369A1

    公开(公告)日：2013-08-08

    申请号：US13803256

    申请日：2013-03-14

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

    IPC: H01L27/105

    CPC classification number: H01L27/105 ,  G11C16/0425 ,  G11C16/0433 ,  H01L21/84 ,  H01L27/108 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/13

    Abstract: The semiconductor device includes a source line, a bit line, a first signal line, a second signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line, a second driver circuit electrically connected to the first signal line, a third driver circuit electrically connected to the second signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

    Abstract translation: 半导体器件包括源极线，位线，第一信号线，第二信号线，字线，在源极线和位线之间并联连接的存储器单元;第一驱动器电路，电连接到源极线 位线，电连接到第一信号线的第二驱动电路，与第二信号线电连接的第三驱动电路，以及电连接到字线的第四驱动电路。 存储单元包括第一晶体管，包括第一栅电极，第一源电极和第一漏电极，第二晶体管包括第二栅电极，第二源电极和第二漏极，以及电容器。 第二晶体管包括氧化物半导体材料。

    Semiconductor device
    56.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12160999B2

    公开(公告)日：2024-12-03

    申请号：US17579640

    申请日：2022-01-20

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kiyoshi Kato

    IPC: H10B99/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/06 ,  H01L27/12 ,  H10B12/00 ,  H10B41/20 ,  H10B41/30 ,  H10B41/70

    Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

    Semiconductor device, electronic component, and electronic device
    58.
    发明授权
    Semiconductor device, electronic component, and electronic device 有权

    公开(公告)号：US12119353B2

    公开(公告)日：2024-10-15

    申请号：US18519294

    申请日：2023-11-27

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Tomoaki Atsumi

    IPC: H01L27/12 ,  H01L29/786 ,  H10B12/00

    CPC classification number: H01L27/1225 ,  H01L27/1255 ,  H01L29/7869 ,  H10B12/20

    Abstract: A novel semiconductor device formed with single-polarity circuits using OS transistors is provided. Thus, connection between different layers in a memory circuit is unnecessary. This can reduce the number of connection portions and improve the flexibility of circuit layout and the reliability of the OS transistors. In particular, many memory cells are provided; thus, the memory cells are formed with single-polarity circuits, whereby the number of connection portions can be significantly reduced. Further, by providing a driver circuit in the same layer as the cell array, many wirings for connecting the driver circuit and the cell array can be prevented from being provided between layers, and the number of connection portions can be further reduced. An interposer provided with a plurality of integrated circuits can function as one electronic component.

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