公开(公告)号：US09230970B2

公开(公告)日：2016-01-05

申请号：US14595692

申请日：2015-01-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Shuhei Nagatsuka

IPC: H01L27/088 ,  H01L27/11 ,  H01L27/06 ,  H01L27/12 ,  H01L49/02 ,  G11C16/04 ,  H01L27/115

CPC classification number: H01L27/1108 ,  G11C16/0408 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

Abstract: A semiconductor device with a novel structure is provided in which stored data can be held even when power is not supplied and the number of writing is not limited. The semiconductor includes a second transistor and a capacitor over a first transistor. The capacitor includes a source or drain electrode and a gate insulating layer of the second transistor and a capacitor electrode over an insulating layer which covers the second transistor. The gate electrode of the second transistor and the capacitor electrode overlap at least partly with each other with the insulating layer interposed therebetween. By forming the gate electrode of the second transistor and the capacitor electrode using different layers, an integration degree of the semiconductor device can be improved.

公开(公告)号：US20150311323A1

公开(公告)日：2015-10-29

申请号：US14740688

申请日：2015-06-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: H01L29/66 ,  H01L21/425 ,  H01L27/115 ,  H01L21/441 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/477

CPC classification number: H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

Abstract translation: 提供了包括非易失性存储单元的半导体器件，其中包括包括氧化物半导体的写入晶体管，包括与写入晶体管不同的半导体材料的读取晶体管和电容器。 通过接通写入晶体管并将电位施加到写入晶体管的源极（或电极），电容器的一个电极和读取晶体管的栅电极的节点处，将数据写入存储单元 电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。 此外，当使用p沟道晶体管作为读取晶体管时，读取电位为正电位。

公开(公告)号：US20140269063A1

公开(公告)日：2014-09-18

申请号：US14201068

申请日：2014-03-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shuhei Nagatsuka ,  Hiroki Inoue ,  Takahiko Ishizu ,  Takanori Matsuzaki ,  Yutaka Shionoiri ,  Kiyoshi Kato

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C16/0433 ,  G11C16/08

Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The electrical charge of a bit line is discharged, the potential of the bit line is charged via a transistor for writing data, and the potential of the bit line which is changed by the charging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

Abstract translation: 从具有使用硅的晶体管的存储单元和使用氧化物半导体的晶体管读取多电平数据，而不用根据多电平数据的电平数来切换用于读取多电平数据的信号。 放电位线的电荷，通过用于写入数据的晶体管对位线的电位进行充电，并且通过充电而改变的位线的电位被读取为多电平数据。 通过这样的结构，可以通过仅读取数据的信号的一次切换来读取对应于保持在晶体管的栅极中的数据的电位。

公开(公告)号：US12300752B2

公开(公告)日：2025-05-13

申请号：US16975309

申请日：2019-02-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Hitoshi Kunitake ,  Yoko Tsukamoto

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/66

Abstract: A semiconductor device in which an electrification phenomenon that leads to characteristic fluctuations, element deterioration, abnormality in shape, or dielectric breakdown is inhibited is provided.
The semiconductor device includes a first region and a second region over the same plane. The first region includes a transistor. The second region includes a dummy transistor. The transistor includes a first wiring layer, a semiconductor layer including an oxide and provided above the first wiring layer, a second wiring layer provided above the semiconductor layer, and a third wiring layer provided above the second wiring layer. The dummy transistor has the same area as one or more selected from the first wiring layer, the second wiring layer, the semiconductor layer, and the third wiring layer.

公开(公告)号：US12069846B2

公开(公告)日：2024-08-20

申请号：US17424621

申请日：2019-11-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Tatsuya Onuki ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: H10B12/00 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786

CPC classification number: H10B12/00 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/78651 ,  H01L29/7869

Abstract: A novel memory device is provided. Over a driver circuit layer, N memory layers (N is a natural number greater than or equal to 2) including a plurality of memory cells provided in a matrix are stacked. The memory cell includes two transistors and one capacitor. An oxide semiconductor is used as a semiconductor included in the transistor. The memory cell is electrically connected to a write word line, a selection line, a capacitor line, a write bit line, and a read bit line. The write bit line and the read bit line extend in the stacking direction, whereby the signal propagation distance from the memory cell to the driver circuit layer is shortened.

公开(公告)号：US11948626B2

公开(公告)日：2024-04-02

申请号：US17439876

申请日：2020-03-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiya Saito ,  Yuto Yakubo ,  Tatsuya Onuki ,  Shuhei Nagatsuka

IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/4097 ,  H01L29/786 ,  H10B12/00

CPC classification number: G11C11/4097 ,  G11C11/4091 ,  H01L29/7869 ,  H10B12/30 ,  H10B12/50

Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line. The first correction circuit has a function of holding a voltage corresponding to a threshold voltage of the second transistor in the gate of the second transistor.

公开(公告)号：US11410716B2

公开(公告)日：2022-08-09

申请号：US16962309

申请日：2019-01-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Hitoshi Kunitake

IPC: G11C8/00 ,  G11C11/408 ,  H01L27/108

Abstract: A novel storage device and a novel semiconductor device are provided.
In the storage device, a cell array including a plurality of memory cells is stacked above a control circuit, and the cell array operates separately in a plurality of blocks. Furthermore, a plurality of electrodes are included between the control circuit and the cell array. The electrode is provided for a corresponding block to overlap with the block, and a potential of the electrode can be changed for each block. The electrode has a function of aback gate of a transistor included in the memory cell, and a potential of the electrode is changed for each block, whereby the electrical characteristics of the transistor included in the memory cell can be changed. Moreover, the electrode can reduce noise caused in the control circuit.

公开(公告)号：US11031403B2

公开(公告)日：2021-06-08

申请号：US16605548

申请日：2018-04-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Daisuke Matsubayashi ,  Kiyoshi Kato ,  Katsuaki Tochibayashi ,  Shuhei Nagatsuka

IPC: H01L27/108 ,  H01L27/1156 ,  H01L27/06 ,  H01L29/786 ,  H01L21/311 ,  H01L27/32 ,  H01L27/12

Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a first transistor, a second transistor, a first capacitor, and a second capacitor. The first transistor includes an oxide over a first insulator, a second insulator over the oxide, a first conductor over the second insulator, a third insulator over the first conductor, a fourth insulator in contact with the second insulator, the first conductor, and the third insulator, and a fifth insulator in contact with the fourth insulator. The second transistor includes an oxide over the first insulator, a sixth insulator over the oxide, a second conductor over the sixth insulator, a seventh insulator over the second conductor, an eighth insulator in contact with the sixth insulator, the second conductor, and the seventh insulator, and a ninth insulator in contact with the eighth insulator. The first capacitor includes an oxide, a tenth insulator over the oxide, and a third conductor over the tenth insulator. The second capacitor includes an oxide, an eleventh insulator over the oxide, and a fourth conductor over the eleventh insulator.

公开(公告)号：US10910884B2

公开(公告)日：2021-02-02

申请号：US16876082

申请日：2020-05-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Akihiro Kimura

IPC: H02J7/00 ,  H02J50/40 ,  H02J50/10 ,  H02J50/27 ,  H04B1/3883 ,  H01M10/44

Abstract: An electric power charge and discharge system for an electronic device having a battery, by which the electronic device can be used for a long period of time. In a wireless communication device including a wireless driving portion including a first battery and a wireless charging portion including a second battery, the first battery is charged by electric power from a fixed power supply and the second battery is charged by using electromagnetic waves existing in an external space. Further, the first battery and the second battery are discharged alternately, and during a period in which the first battery is discharged, the second battery is charged.

公开(公告)号：US10388364B2

公开(公告)日：2019-08-20

申请号：US15695128

申请日：2017-09-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Shuhei Nagatsuka

IPC: G11C7/14 ,  G11C11/419 ,  G11C7/22 ,  G11C16/04 ,  G11C16/24 ,  G11C16/28 ,  H01L27/11529 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4099 ,  H01L29/786 ,  G11C7/06 ,  H01L27/1156

Abstract: A memory device includes a memory cell, a replica cell, a read circuit, a write wordline, a read wordline, a dummy read wordline, a write bitline, a read bitline, a reference bitline, a sourceline, and a first wiring. The memory cell is electrically connected to the write wordline, the read wordline, the write bitline, the read bitline, and the sourceline. The read circuit outputs a potential based on the result of comparing the potential of the reference bitline and the potential of the read bitline. The replica cell includes a first transistor and a second transistor. The first transistor and the second transistor are electrically connected to each other in series between the bitline and the sourceline. A gate of the first transistor and a gate of the second transistor are electrically connected to a dummy read wordline and the first wiring, respectively.