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59 条记录 (耗时 0.021 秒)

    Semiconductor device testing method and testing equipment
    51.
    发明授权
    Semiconductor device testing method and testing equipment 有权
    半导体器件测试方法和测试设备

    公开(公告)号：US07199600B2

    公开(公告)日：2007-04-03

    申请号：US11078352

    申请日：2005-03-14

    申请人： Hitoshi Izuru ,  Kazuhiro Tashiro

    发明人： Hitoshi Izuru ,  Kazuhiro Tashiro

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2849

    摘要： A burn-in testing method to perform tests with a semiconductor device operated in an atmosphere at a prescribed temperature characterized in that operation instruction signals instructing an operation of the semiconductor device are repeatedly supplied while supplying power to the semiconductor device, and increases and decreases in a power supply current corresponding to the operation instruction signals are counted.

    摘要翻译： 一种老化测试方法，用于在规定温度的大气中操作的半导体器件进行测试，其特征在于，在向半导体器件供电的同时，重复地提供指示半导体器件的操作的操作指令信号，并且增加和减少 对与操作指示信号相对应的电源电流进行计数。

    Semiconductor device testing method and testing equipment
    52.
    发明申请
    Semiconductor device testing method and testing equipment 有权
    半导体器件测试方法和测试设备

    公开(公告)号：US20060061379A1

    公开(公告)日：2006-03-23

    申请号：US11078352

    申请日：2005-03-14

    申请人： Hitoshi Izuru ,  Kazuhiro Tashiro

    发明人： Hitoshi Izuru ,  Kazuhiro Tashiro

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2849

    摘要： A burn-in testing method to perform tests with a semiconductor device operated in an atmosphere at a prescribed temperature characterized in that operation instruction signals instructing an operation of the semiconductor device are repeatedly supplied while supplying power to the semiconductor device, and increases and decreases in a power supply current corresponding to the operation instruction signals are counted.

    摘要翻译： 一种老化测试方法，用于在规定温度的大气中操作的半导体器件进行测试，其特征在于，在向半导体器件供电的同时，重复地提供指示半导体器件的操作的操作指令信号，并且增加和减少 对与操作指示信号相对应的电源电流进行计数。

    Attachment structure of semiconductor device socket
    53.
    发明授权
    Attachment structure of semiconductor device socket 失效
    半导体器件插座的附件结构

    公开(公告)号：US06203332B1

    公开(公告)日：2001-03-20

    申请号：US09461425

    申请日：1999-12-16

    申请人： Kazuhiro Tashiro ,  Daisuke Koizumi

    发明人： Kazuhiro Tashiro ,  Daisuke Koizumi

    IPC分类号： H01R1200

    CPC分类号： G01R1/0483

    摘要： An attachment structure between a semiconductor device socket and a test circuit substrate is provided. The semiconductor device socket includes a socket body and a contact film disposed therein. Extension conductive wires extended from a contact portion to be connected to a semiconductor device are formed on the contact film. The contact film is also provided with socket connectors connected to the extension conductive wires. The test circuit substrate is provided with circuit substrate connectors corresponding to the socket connectors. The socket connectors and the circuit substrate connectors are in a male-female connector relationship.

    摘要翻译： 提供半导体器件插座和测试电路基板之间的连接结构。 半导体器件插座包括插座主体和设置在其中的接触膜。 在接触膜上形成从连接到半导体器件的接触部分延伸的延伸导线。 接触膜还设置有连接到延伸导电线的插座连接。 测试电路基板设置有对应于插座连接器的电路基板连接器。 插座连接器和电路基板连接器处于公 - 母连接器关系。

    Integrated circuit carrier having lead-socket array with various inner dimensions
    54.
    发明授权
    Integrated circuit carrier having lead-socket array with various inner dimensions 失效
    集成电路载体，具有各种内部尺寸的导线插座阵列

    公开(公告)号：US5668407A

    公开(公告)日：1997-09-16

    申请号：US673095

    申请日：1996-07-01

    申请人： Kazuhiro Tashiro ,  Tetsushi Wakabayashi

    发明人： Kazuhiro Tashiro ,  Tetsushi Wakabayashi

    IPC分类号： H01L23/00 ,  G01R1/04 ,  H05K3/30 ,  H05K7/10 ,  H01L23/48

    CPC分类号： G01R1/0433 ,  H05K7/1084 ,  H05K3/306

    摘要： An IC carrier for electric testing of an IC package enables an IC package to be loaded on or unloaded from it smoothly without bending any of closely arranged fine leads, and prevents the leads from being deformed by falling impact when it is dropped. The IC carrier for an IC package, having an array of leads, comprises an array of sockets for mating with the array of leads, wherein selected one of the sockets differs in clearance between a width of each of the sockets and a width of each of the leads to be mated from the other ones in a cross section of an array. For instance, an array of sockets having holes to mate with leads having a single diameter of an IC package are arranged so that inner diameters of the holes in an outer part of the array is larger than those in a central part of the array. The technique is applicable to both a flat IC package (QFP or SOP) and a pin grid array IC package (PGA).

    摘要翻译： 用于IC封装的电测试的IC载体使得IC封装能够平滑地装载或卸载IC封装，而不会弯曲任何紧密排列的细小引线，并且防止引线在跌落时由于冲击而变形。 用于具有引线阵列的IC封装的IC载体包括用于与引线阵列配合的插座阵列，其中插座中的选定一个插座间隙在每个插座的宽度和每个插座的宽度之间的间隙 导线与阵列的横截面中的其他导线相交。 例如，具有与IC封装的单一直径的引线相配合的孔的插座阵列被布置成使得阵列的外部部分中的孔的内径大于阵列的中心部分中的孔的内径。 该技术适用于扁平IC封装（QFP或SOP）和引脚格栅阵列IC封装（PGA）。

    Semiconductor integrated circuit device and test method thereof
    56.
    发明申请
    Semiconductor integrated circuit device and test method thereof 失效
    半导体集成电路器件及其测试方法

    公开(公告)号：US20070170425A1

    公开(公告)日：2007-07-26

    申请号：US11411877

    申请日：2006-04-27

    申请人： Kazuhiro Tashiro ,  Hitoshi Izuru

    发明人： Kazuhiro Tashiro ,  Hitoshi Izuru

    IPC分类号： H01L23/58

    CPC分类号： H01L22/32 ,  G01R31/2863 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/3512 ,  H01L2924/00

    摘要： The present invention provides a high-quality semiconductor integrated circuit device, where the semiconductor integrated circuit device, a SiP or especially PoP semiconductor integrated circuit device, enables a simultaneous testing of the reliability of multiple upper and lower semiconductor integrated circuit elements; it also enables a testing of only the non-defective element in case the other is determined defective; moreover, only the defective unit is exchangeable with a non-defective unit. The semiconductor integrated circuit device of the present invention contains multiple semiconductor integrated circuit elements, e.g. semiconductor integrated circuit devices 14 and 16, and a circuit board 12 which relays the respective semiconductor integrated circuit elements 14 and 16, and at least a part of the circuit board 12, e.g. test pads 13, can be electrically connected to an external test apparatus when the semiconductor integrated circuit devices 14 and 16 are electrically connected to the circuit board 12.

    摘要翻译： 本发明提供了一种高质量的半导体集成电路器件，其中半导体集成电路器件，SiP或特别是PoP半导体集成电路器件能够同时测试多个上下半导体集成电路元件的可靠性; 它还能够在另一个被确定有缺陷的情况下仅测试无缺陷元件; 此外，只有有缺陷的单元可与无缺陷单元交换。 本发明的半导体集成电路器件包含多个半导体集成电路元件，例如 半导体集成电路器件14和16以及中继各个半导体集成电路元件14和16以及电路板12的至少一部分的电路板12，例如， 当半导体集成电路器件14和16电连接到电路板12时，测试焊盘13可以电连接到外部测试装置。

    Barrel temperature control system for injection molding machine
    58.
    发明授权
    Barrel temperature control system for injection molding machine 失效
    桶注塑机温控系统

    公开(公告)号：US5597588A

    公开(公告)日：1997-01-28

    申请号：US413157

    申请日：1995-03-29

    申请人： Tsuginobu Totani ,  Kazuhiro Tashiro ,  Shogo Ishibashi ,  Kiyoshi Sasaki

    发明人： Tsuginobu Totani ,  Kazuhiro Tashiro ,  Shogo Ishibashi ,  Kiyoshi Sasaki

    IPC分类号： B29C45/74 ,  B29C45/78

    CPC分类号： B29C45/78

    摘要： The barrel temperature control apparatus for an injection molding machine can execute the barrel temperature control in such a way as to optimize the disturbance suppression characteristics. The temperature control section 7 comprises the manipulated variable addition and subtraction section 14 at the rear stage of the PiD control section 12 in such a way that the barrel temperature of the injection molding machine 1 can be controlled under both feedback and feed-forward. Further, when the same products are molded continuously, the barrel temperature is feed-forward controlled on the basis of the learned change manipulated variable.

    摘要翻译： 用于注射成型机的桶式温度控制装置可以以优化干扰抑制特性的方式执行机筒温度控制。 温度控制部7包括在PiD控制部12的后级的操作量可变加减部14，使得可以在反馈和前馈两者下控制注塑机1的机筒温度。 此外，当相同的产品连续模制时，基于学习的变化操作变量来控制机筒温度是前馈的。