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    Secure Master and Secure Guest Endpoint Security Firewall
    53.
    发明申请
    Secure Master and Secure Guest Endpoint Security Firewall 审中-公开
    安全主控和安全访客端点安全防火墙

    公开(公告)号：US20140143849A1

    公开(公告)日：2014-05-22

    申请号：US14062002

    申请日：2013-10-24

    Applicant: Texas Instruments Incorporated

    Inventor： Timothy D. Anderson ,  Joseph R. M. Zbiciak ,  Matthew D. Pierson ,  Kai Chirca

    IPC: H04L29/06

    CPC classification number: G06F21/78 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0835 ,  G06F12/0842 ,  G06F12/1081 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/42 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621 ,  H04L63/0263 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    Abstract: This invention is a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure master and n secure guests. The firewall includes one secure region for secure master and one secure region for secure guests. The SM region only allows access from the secure master and the SG region allows accesses from any secure transaction. Finally, the non-secure region can be implemented two ways. In a first option, non-secure regions may be accessed only upon non-secure transactions. In a second option, non-secure regions may be accessed any processing core. In this second option, the access is downgraded to a non-secure access if the security identity is secure master or secure guest. If the two security levels are not needed the secure master can unlock the SM region to allow any secure guest access to the SM region.

    Abstract translation: 本发明是具有安全层级的安全防火墙，包括：安全主机（SM）; 安全客人（SG）; 和非安全（NS）。 有一个安全的主人和n个安全的客人。 防火墙包括一个用于安全主控的安全区域和一个用于安全访客的安全区域。 SM区域仅允许从安全主机访问，并且SG区域允许来自任何安全事务的访问。 最后，非安全区域可以实现两种方式。 在第一个选项中，只有在非安全事务时才可以访问非安全区域。 在第二个选项中，非安全区域可以被访问任何处理核心。 在第二个选项中，如果安全身份是安全主机或安全访客，则访问权限降级到非安全访问。 如果不需要两个安全级别，则安全主机可以解锁SM区域，以允许任何安全访客访问SM区域。

    FLEXIBLE ARBITRATION SCHEME FOR MULTI ENDPOINT ATOMIC ACCESSES IN MULTICORE SYSTEMS
    54.
    发明申请
    FLEXIBLE ARBITRATION SCHEME FOR MULTI ENDPOINT ATOMIC ACCESSES IN MULTICORE SYSTEMS 有权
    用于多系统中多端点原子访问的灵活仲裁方案

    公开(公告)号：US20140143486A1

    公开(公告)日：2014-05-22

    申请号：US14061470

    申请日：2013-10-23

    Applicant: Texas Instruments Incorporated

    Inventor： Kai Chirca ,  Matthew D. Pierson

    IPC: G06F3/06

    CPC classification number: G06F12/084 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0683 ,  G06F11/1064 ,  G06F13/1652 ,  G06F13/1668 ,  G06F2212/1016 ,  G06F2212/60

    Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.

    Abstract translation: 描述的MSMC（多核共享内存控制器）是一种旨在管理多处理器内核，其他母盘外设或DMA之间的流量的模块，以及多核SoC中的EMIF（外部存储器间隔）。 本发明在仲裁事务之前统一属于从属方的所有事务大小，以便降低仲裁过程的复杂性，并在所有主机之间提供最佳的带宽管理。 每个缓存行访问分配两个连续的插槽，以自动保证单个高速缓存行内所有事务的原子性。 消除了对特定SRAM的所有存储体之间同步的需要，因为通过分配背靠背槽来实现同步。

    DISTRIBUTED DATA RETURN BUFFER FOR COHERENCE SYSTEM WITH SPECULATIVE ADDRESS SUPPORT
    55.
    发明申请
    DISTRIBUTED DATA RETURN BUFFER FOR COHERENCE SYSTEM WITH SPECULATIVE ADDRESS SUPPORT 有权
    分布式数据返回缓冲器，用于具有分析地址支持的协调系统

    公开(公告)号：US20140115273A1

    公开(公告)日：2014-04-24

    申请号：US14061508

    申请日：2013-10-23

    Applicant: Texas Instruments Incorporated

    Inventor： Kai Chirca ,  Matthew D. Pierson

    IPC: G06F12/08

    CPC classification number: G06F12/0831 ,  G06F11/2289 ,  G06F12/0284 ,  G06F13/1668 ,  G06F13/1673 ,  G06F2212/6042

    Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace)in a multicore SoC. Each processor has an associated return buffer allowing out of order responses of memory read data and cache snoop responses to ensure maximum bandwidth at the endpoints, and all endpoints receive status messages to simplify the return queue.

    Abstract translation: 描述的MSMC（多核共享存储器控制器）是一种旨在管理多处理器内核，其他母盘外设或DMA之间流量的模块，以及多核SoC中的EMIF（外部存储器间隔）。 每个处理器都有一个关联的返回缓冲区，允许存储器读取数据和高速缓存侦听响应的无序响应，以确保端点处的最大带宽，并且所有端点接收状态消息以简化返回队列。

    OPTIONAL ACKNOWLEDGEMENT FOR OUT-OF-ORDER COHERENCE TRANSACTION COMPLETION
    56.
    发明申请
    OPTIONAL ACKNOWLEDGEMENT FOR OUT-OF-ORDER COHERENCE TRANSACTION COMPLETION 有权
    用于不及格相关交易完成的可选确认

    公开(公告)号：US20140115266A1

    公开(公告)日：2014-04-24

    申请号：US14056775

    申请日：2013-10-17

    Applicant: Texas Instruments Incorporated

    Inventor： Daniel B Wu ,  Matthew D Pierson ,  Kai Chirca ,  Timothy D Anderson

    IPC: G06F12/08

    CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

    Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

    Abstract translation: 为了能够有效跟踪事务，使用确认期望信号来给缓存一致互连提供一个交易是否需要连贯的所有权跟踪的提示。 该信号通知高速缓存相干互连，以便在读/写传输完成时期望来自发起主机的所有权转移确认信号。 因此，高速缓存相干互连可以在其一致性点继续跟踪事务，直到在必要时从发起主机接收到确认。

    Multi Processor Multi Domain Conversion Bridge with Out of Order Return Buffering
    57.
    发明申请
    Multi Processor Multi Domain Conversion Bridge with Out of Order Return Buffering 有权
    多处理器多域转换桥与乱序返回缓冲

    公开(公告)号：US20140115210A1

    公开(公告)日：2014-04-24

    申请号：US14056729

    申请日：2013-10-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai Chirca ,  Daniel B. Wu ,  Matthew D. Pierson ,  Timothy D. Anderson

    IPC: G06F13/16

    CPC classification number: G06F12/0831 ,  G06F12/0815 ,  G06F13/1689 ,  G06F13/4013 ,  G06F13/4027 ,  G06F2212/6042 ,  G06F2212/621

    Abstract: An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain—master and interconnect. The asynchronous bridge is aware of the bus protocols used by each individual processor within the attached subsystem, and can perform the appropriate protocol conversion on each processor's transactions to adapt the transaction to/from the bus protocol used by the interconnect.

    Abstract translation: 在高速缓存一致主机和相干系统互连之间实现异步双域网桥。 该桥具有两个半部分，每个时钟/电源下降域主和互连中一个。 异步网桥了解连接子系统内每个处理器所使用的总线协议，并且可以对每个处理器的事务执行适当的协议转换，以使交易与互连使用的总线协议相适应。

    Nested loop control
    60.
    发明授权
    Nested loop control 有权

    公开(公告)号：US11972236B1

    公开(公告)日：2024-04-30

    申请号：US17942239

    申请日：2022-09-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L Davis

    IPC: G06F8/41 ,  G06F5/06 ,  G06F9/30

    CPC classification number: G06F8/433 ,  G06F5/06 ,  G06F9/30065

    Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

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