公开(公告)号：US11984418B2

公开(公告)日：2024-05-14

申请号：US17884284

申请日：2022-08-09

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Frank Pavone ,  Patrick Francis Thompson

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02317 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03502 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05618 ,  H01L2224/05647 ,  H01L2224/11424 ,  H01L2224/1145 ,  H01L2224/11848 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13618 ,  H01L2224/13647 ,  H01L2924/0132

Abstract: A method for manufacturing a package includes positioning a copper layer above a die. A zinc layer is positioned on the copper layer. The zinc and copper layers are then heated to produce a brass layer, the brass layer abutting the copper layer. Further, a polymer layer is positioned abutting the brass layer.

公开(公告)号：US11854933B2

公开(公告)日：2023-12-26

申请号：US17138541

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Archana Venugopal ,  Daniel Lee Revier

IPC: H01L23/373 ,  H01L23/532 ,  H01L21/683 ,  H01L21/3205 ,  H01L21/78

CPC classification number: H01L23/373 ,  H01L21/32051 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/53209

Abstract: In described examples, a semiconductor wafer with a thermally conductive surface layer comprises a bulk semiconductor layer having a first surface and a second surface, circuitry on the first surface, a metallic layer attached to the first surface or the second surface, and a graphene layer attached to the metallic layer. The first surface opposes the second surface. The metallic layer comprises a transition metal.

公开(公告)号：US11848258B2

公开(公告)日：2023-12-19

申请号：US17139985

申请日：2020-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Bernardo Gallegos

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49582 ,  H01L21/4825 ,  H01L21/4835 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/4952 ,  H01L23/49513 ,  H01L23/562 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/48655 ,  H01L2224/48739 ,  H01L2224/48755 ,  H01L2224/48839 ,  H01L2224/48855 ,  H01L2224/85205 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/15747 ,  H01L2924/35121

Abstract: A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.

公开(公告)号：US11594504B2

公开(公告)日：2023-02-28

申请号：US17234429

申请日：2021-04-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/00 ,  H01L21/78

Abstract: A packaged semiconductor die includes a semiconductor die coupled to a die pad. The semiconductor die has a front side containing copper leads, a copper seed layer coupled to the copper leads, and a nickel alloy coating coupled to the copper seed layer. The nickel alloy includes tungsten and cerium (NiWCe). The packaged semiconductor die may also include wire bonds coupled between leads of a lead frame and the copper leads of the semiconductor die. In addition, the packaged semiconductor die may be encapsulated in molding compound. A method for fabricating a packaged semiconductor die. The method includes forming a copper seed layer over the copper leads of the semiconductor die. In addition, the method includes coating the copper seed layer with a nickel alloy. The method also includes singulating the semiconductor wafer to create individual semiconductor die and placing the semiconductor die onto a die pad of a lead frame.

公开(公告)号：US11063120B2

公开(公告)日：2021-07-13

申请号：US16232123

申请日：2018-12-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Luigi Colombo ,  Archana Venugopal ,  Benjamin Stassen Cook ,  Nazila Dadvand

IPC: H01L29/16 ,  H01L21/768 ,  C01B32/194 ,  H01L23/532 ,  H01L27/06 ,  H01L29/06 ,  C23C16/26 ,  H01L21/02 ,  C01B32/184 ,  C25D11/00 ,  C23C16/02 ,  B05D1/00 ,  H01L23/00

Abstract: A structure includes a metal layer and a plurality of interconnected unit cells forming a lattice contained at least partly within the metal layer, including at least a first unit cell formed of first interconnected graphene tubes, and a second unit cell formed of second interconnected graphene tubes, wherein the metal layer protrudes through holes within the lattice.

公开(公告)号：US20210210419A1

公开(公告)日：2021-07-08

申请号：US17210392

申请日：2021-03-23

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand

IPC: H01L23/495 ,  H01L23/28 ,  H05K3/34 ,  H01L23/00 ,  H01L23/532

Abstract: A device and method for fabrication thereof is provided which results in corrosion resistance of metal flanges (802) of a semiconductor package, such as a quad flat no-lead package (QFN). Using metal electroplating (such as electroplating of nickel (Ni) or nickel alloys on copper flanges of the QFN package), corrosion resistance for the flanges is provided using a process that allows an electric current to reach the entire backside of a substrate (102) to permit electroplating. In addition, the method may be used to directly connect a semiconductor die (202) to the metal substrate (102) of the package.

公开(公告)号：US11011488B2

公开(公告)日：2021-05-18

申请号：US16660187

申请日：2019-10-22

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/00 ,  H01L23/495 ,  B23K1/00 ,  C25D7/12 ,  C25D3/22 ,  B23K101/36 ,  C25D3/12

Abstract: A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.

公开(公告)号：US11011483B2

公开(公告)日：2021-05-18

申请号：US15901631

申请日：2018-02-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/00 ,  H01L21/78

Abstract: A packaged semiconductor die includes a semiconductor die coupled to a die pad. The semiconductor die has a front side containing copper leads, a copper seed layer coupled to the copper leads, and a nickel alloy coating coupled to the copper seed layer. The nickel alloy includes tungsten and cerium (NiWCe). The packaged semiconductor die may also include wire bonds coupled between leads of a lead frame and the copper leads of the semiconductor die. In addition, the packaged semiconductor die may be encapsulated in molding compound. A method for fabricating a packaged semiconductor die. The method includes forming a copper seed layer over the copper leads of the semiconductor die. In addition, the method includes coating the copper seed layer with a nickel alloy. The method also includes singulating the semiconductor wafer to create individual semiconductor die and placing the semiconductor die onto a die pad of a lead frame. In addition the method includes wire bonding the leads of a lead frame to the copper leads of the semiconductor die and then encapsulating the die in molding compound.

公开(公告)号：US20210028060A1

公开(公告)日：2021-01-28

申请号：US17038947

申请日：2020-09-30

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/532

Abstract: Described examples provide microelectronic devices and fabrication methods, including fabricating a contact structure by forming a titanium or titanium tungsten barrier layer on a conductive feature, forming a tin seed layer on the barrier layer, forming a copper structure on the seed layer above the conductive feature of the wafer or die, heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure, removing the seed layer using an etching process that selectively removes an exposed portion of the seed layer, and removing an exposed portion of the barrier layer.

公开(公告)号：US20200381517A1

公开(公告)日：2020-12-03

申请号：US16995563

申请日：2020-08-17

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Luigi Colombo ,  Nazila Dadvand ,  Archana Venugopal

IPC: H01L29/15 ,  H01L29/16 ,  H01L29/808 ,  H01L29/423

Abstract: A switchable array includes: a microstructure of interconnected units formed of graphene tubes with open spaces in the microstructure bounded by the graphene tubes; at least one JFET gate in at least one of the graphene tubes; and a control line having an end connected to the at least one JFET gate. The control line extends to a periphery of the microstructure.