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    MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY DEVICE
    53.
    发明申请
    MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY DEVICE 有权

    公开(公告)号：US20170222135A1

    公开(公告)日：2017-08-03

    申请号：US15502442

    申请日：2015-07-29

    Applicant: TOHOKU UNIVERSITY

    Inventor： Shunsuke Fukami ,  Chaoling Zhang ,  Tetsuro Anekawa ,  Hideo Ohno ,  Tetsuo Endoh

    IPC: H01L43/08 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

    CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  H01L27/105 ,  H01L27/228 ,  H01L29/82 ,  H01L43/02 ,  H01L43/10

    Abstract: A magnetoresistance effect element (100) includes a heavy metal layer (11) that includes a heavy metal and that is formed to extend in a first direction, a recording layer (12) that includes a ferromagnetic material and that is provided adjacent to the heavy metal layer (11), a barrier layer (13) that includes an insulating material and that is provided on the recording layer (12) with being adjacent to a surface of the recording layer (12) opposite to the heavy metal layer (11), and a reference layer (14) that includes a ferromagnetic material and that is provided adjacent to a surface of the barrier layer (13), the surface being opposite to the recording layer (12). The direction of the magnetization of the reference layer (14) has a component substantially fixed in the first direction, and the direction of the magnetization of the recording layer (12) has a component variable in the first direction. A current having a direction same as the first direction is introduced to the heavy metal layer (11) to thereby enable the magnetization of the recording layer (12) to be inverted.

    MEMORY CIRCUIT
    54.
    发明申请
    MEMORY CIRCUIT 有权
    存储器电路

    公开(公告)号：US20160225428A1

    公开(公告)日：2016-08-04

    申请号：US15023101

    申请日：2014-09-18

    Applicant: TOHOKU UNIVERSITY

    Inventor： Takashi Ohsawa ,  Tetsuo Endoh

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1697 ,  G11C13/003 ,  G11C14/0081 ,  G11C2013/0071 ,  G11C2213/74 ,  G11C2213/79

    Abstract: One end of a current path of a second field-effect transistor is connected to a gate of a first field-effect transistor. One end of a magnetic tunnel junction element is connected to one end of a current path of the first field-effect transistor. A first control terminal is connected to another end of the current path of the first field-effect transistor. A second control terminal is connected to another end of the magnetic tunnel junction element. A third control terminal is connected to another end of the current path of the second field-effect transistor.

    Abstract translation: 第二场效应晶体管的电流路径的一端连接到第一场效应晶体管的栅极。 磁性隧道结元件的一端连接到第一场效应晶体管的电流通路的一端。 第一控制端子连接到第一场效应晶体管的电流路径的另一端。 第二控制端子连接到磁性隧道结元件的另一端。 第三控制端子连接到第二场效应晶体管的电流通路的另一端。

    MEMORY CELL AND STORAGE DEVICE
    55.
    发明申请
    MEMORY CELL AND STORAGE DEVICE 有权
    存储单元和存储设备

    公开(公告)号：US20160224082A1

    公开(公告)日：2016-08-04

    申请号：US15023066

    申请日：2014-09-18

    Applicant: TOHOKU UNIVERSITY

    Inventor： Takashi Ohsawa ,  Tetsuo Endoh

    IPC: G06F1/26 ,  G11C11/16

    CPC classification number: G06F1/26 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697 ,  G11C14/0081

    Abstract: A memory cell (101) is connected to a word line (WL), a bit line (BL), and a power supply line (PL), and includes a flip-flop storing data based on a change in resistance value of a magnetic tunnel junction element, and, a power gating field-effect transistor including a drain that is one end of a current path connected to the power supply line, and which has another end connected to the flip-flop. The ON and OFF states of the power gating field-effect transistor are controlled based on a control signal applied to a control terminal of the power gating field-effect transistor.

    Abstract translation: 存储单元（101）连接到字线（WL），位线（BL）和电源线（PL），并且包括触发器，其基于磁性电阻值的变化存储数据 隧道结元件，以及电源门控场效应晶体管，其包括作为连接到电源线的电流通路的一端的漏极，并且另一端连接到触发器。 电源门控场效应晶体管的导通和截止状态基于施加到电源门控场效应晶体管的控制端的控制信号来控制。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF PRODUCING THE SAME
    57.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF PRODUCING THE SAME 有权
    半导体集成电路及其制造方法

    公开(公告)号：US20150194436A1

    公开(公告)日：2015-07-09

    申请号：US14600554

    申请日：2015-01-20

    Applicant: TOHOKU UNIVERSITY

    Inventor： Tetsuo Endoh ,  Seo Moon-Sik

    IPC: H01L27/115 ,  H01L29/423

    CPC classification number: H01L27/11556 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/0483 ,  H01L27/088 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/42328 ,  H01L29/66477 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7889

    Abstract: Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell 1 in the semiconductor integrated circuit is provided with: a semiconductor pillar 2 that serves as a channel; a floating gate 5 that circumferentially covers the semiconductor pillar 2 via a tunnel insulation layer 6 on the outer circumference of the semiconductor pillar 2; and a control gate 4 that circumferentially covers the semiconductor pillar via an insulating layer 8 on the outer circumference of the semiconductor pillar 2, and that circumferentially covers the floating gate 5 via an insulating layer 7 on the outer circumference of the floating gate.

    Abstract translation: 提供了一种半导体集成电路，其使用在电池之间没有干扰的新颖的垂直MOS晶体管，其能够使短沟道效应最小化，不具有热电子注入，并且不需要形成浅结 。 还提供了一种制造半导体集成电路的方法。 半导体集成电路中的存储单元1设置有：作为通道的半导体柱2; 通过半导体柱2的外周上的隧道绝缘层6周向地覆盖半导体柱2的浮动栅极5; 以及通过半导体柱2的外周上的绝缘层8周向地覆盖半导体柱的控制栅极4，并且经由浮动栅极的外周上的绝缘层7周向地覆盖浮置栅极5。

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