公开(公告)号：US20240105627A1

公开(公告)日：2024-03-28

申请号：US18525958

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49861 ,  H01L23/5384

Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.

公开(公告)号：US11830745B2

公开(公告)日：2023-11-28

申请号：US17352664

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Wei Chiu ,  Cheng-Hsien Hsieh ,  Hsien-Pin Hu ,  Kuo-Ching Hsu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L21/4853 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L21/56 ,  H01L23/49811 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/13 ,  H01L2224/73204

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

公开(公告)号：US11169207B2

公开(公告)日：2021-11-09

申请号：US16869775

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Chao-Hsiang Yang

IPC: G01R31/28 ,  H01L21/66 ,  H01L23/00 ,  G01R1/04 ,  G01R31/26

Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.

公开(公告)号：US20210313196A1

公开(公告)日：2021-10-07

申请号：US17352664

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Wei Chiu ,  Cheng-Hsien Hsieh ,  Hsien-Pin Hu ,  Kuo-Ching Hsu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/683

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

公开(公告)号：US20210242173A1

公开(公告)日：2021-08-05

申请号：US17233895

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ming Chen ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Wen-Hsin Wei

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: A semiconductor device and a method of forming the device are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.

公开(公告)号：US20190057912A1

公开(公告)日：2019-02-21

申请号：US16148169

申请日：2018-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzuan-Horng Liu ,  Chen-Hua Yu ,  Hsien-Pin Hu ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC: H01L21/66 ,  H01L21/48 ,  H01L23/58 ,  G01R1/073 ,  H01L23/522 ,  H01L23/498 ,  H01L21/683 ,  H01L21/56

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

公开(公告)号：US10163853B2

公开(公告)日：2018-12-25

申请号：US15794277

申请日：2017-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Hsin Wei ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Wei-Ming Chen

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H05K3/36 ,  H01L25/18

Abstract: Formation methods of a chip package are provided. The method includes bonding a first chip structure and a second chip structure over a substrate. The method also includes forming a release film to cover top surfaces of the first chip structure and the second chip structure. The method further includes forming a package layer to surround the first chip structure and the second chip structure after the formation of the release film. In addition, the method includes removing the release film such that the top surface of the first chip structure, the top surface of the second chip structure, and a top surface of the package layer are exposed.

公开(公告)号：US20170212167A1

公开(公告)日：2017-07-27

申请号：US15481891

申请日：2017-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Chao-Hsiang Yang

IPC: G01R31/28 ,  G01R1/04 ,  H01L23/00 ,  G01R31/26

CPC classification number: G01R31/2896 ,  G01R1/0416 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/0614 ,  H01L2224/0616 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16238 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

Abstract: A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.

公开(公告)号：US09618572B2

公开(公告)日：2017-04-11

申请号：US15170062

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Chao-Hsiang Yang

IPC: H01R31/00 ,  G01R31/28 ,  H01L21/66 ,  G01R1/04 ,  G01R31/26 ,  H01L23/00

CPC classification number: G01R31/2896 ,  G01R1/0416 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/0614 ,  H01L2224/0616 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16238 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

Abstract: A package includes a semiconductor chip. The semiconductor chip includes a test pad, and a plurality of microbump pads, wherein each microbump pad of the plurality of microbump pads is electrically connected to the test pad. The package further includes a substrate; and a plurality of microbumps configured to electrically connect the semiconductor chip to the substrate, wherein each microbump of the plurality of microbumps is electrically connected to a corresponding microbump pad of the plurality of microbump pads. The package further includes a package substrate, wherein the package substrate comprises a bump pad, wherein an area of the bump pad is greater than a combined area of the test pad and the plurality of microbump pads. The package further includes a bump configured to electrically connect the substrate to the package substrate.