公开(公告)号：US11725278B2

公开(公告)日：2023-08-15

申请号：US16723643

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mo Lin ,  Yi-Hung Lin ,  Jr-Hung Li ,  Tze-Liang Lee ,  Ting-Gang Chen ,  Chung-Ting Ko

IPC: C23C16/455 ,  H01J37/32 ,  C23C16/509 ,  H01L21/02 ,  H01L21/285

CPC classification number: C23C16/45536 ,  C23C16/45551 ,  C23C16/45565 ,  C23C16/509 ,  H01J37/3244 ,  H01J37/32091 ,  H01J37/32357 ,  H01J37/32366 ,  H01J37/32449 ,  H01J37/32522 ,  H01J37/32532 ,  H01J37/32541 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/02274 ,  H01L21/28556

Abstract: A system and method for plasma enhanced deposition processes. An exemplary semiconductor manufacturing system includes a susceptor configured to hold a semiconductor wafer and a sector disposed above the susceptor. The sector includes a first plate and an overlying second plate, operable to form a plasma there between. The first plate includes a plurality of holes extending through the first plate, which vary in at least one of diameter and density from a first region of the first plate to a second region of the first plate.

公开(公告)号：US11705332B2

公开(公告)日：2023-07-18

申请号：US17150403

申请日：2021-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen Kuo ,  Chih-Cheng Liu ,  Ming-Hui Weng ,  Jia-Lin Wei ,  Yen-Yu Chen ,  Jr-Hung Li ,  Yahru Cheng ,  Chi-Ming Yang ,  Tze-Liang Lee ,  Ching-Yu Chang

IPC: H01L21/00 ,  H01L21/027 ,  H01L21/02

CPC classification number: H01L21/0275 ,  H01L21/0228 ,  H01L21/02362

Abstract: A method of forming a pattern in a photoresist layer includes forming a photoresist layer over a substrate, and reducing moisture or oxygen absorption characteristics of the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

公开(公告)号：US20230154843A1

公开(公告)日：2023-05-18

申请号：US17674459

申请日：2022-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Zhong Chen ,  JeiMing Chen ,  Tze-Liang Lee

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L28/92 ,  H01L28/91 ,  H01L23/5226 ,  H01L21/76877 ,  H01L21/76829

Abstract: A semiconductor device includes: a substrate; an interconnect structure over the substrate; an etch stop layer over the interconnect structure; and metal-insulator-metal (MIM) capacitors over the etch stop layer. The MIM capacitors includes: a bottom electrode extending along the etch stop layer, where the bottom electrode has a layered structure that includes a first conductive layer, a second conductive layer, and a third conductive layer between the first conductive layer and the second conductive layer, where the first conductive layer and the second conductive layer include a first material, and the third conductive layer includes a second material different from the first material; a first dielectric layer over the bottom electrode; a middle electrode over the first dielectric layer, where the middle electrode has the layered structure; a second dielectric layer over the middle electrode; and a top electrode over the second dielectric layer.

公开(公告)号：US20230154837A1

公开(公告)日：2023-05-18

申请号：US17651665

申请日：2022-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Jen Sung ,  Guan-Yao Tu ,  Tze-Liang Lee

IPC: H01L23/498 ,  H01L23/367 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/367 ,  H01L21/4857

Abstract: A method includes forming a first bond layer on a first wafer, and forming a first thermal conductive channel extending into the first bond layer. The first thermal conductive channel has a first thermal conductivity value higher than a second thermal conductivity value of the first bond layer. The method further includes forming a second bond layer on a second wafer, and forming a second thermal conductive channel extending into the second bond layer. The second thermal conductive channel has a third thermal conductivity value higher than a fourth thermal conductivity value of the second bond layer. The first wafer is bonded to the second wafer, and the first thermal conductive channel at least physically contacts the second thermal conductive channel. An interconnect structure is formed over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.

公开(公告)号：US20230121210A1

公开(公告)日：2023-04-20

申请号：US17710457

申请日：2022-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ren Wang ,  Jen Hung Wang ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L23/535 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes forming a metal line extending through a first dielectric layer, the metal line being electrically coupled to a transistor; selectively depositing a sacrificial material over the metal line; selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material; selectively depositing a second dielectric material over the first dielectric material; removing the sacrificial material to form a first recess exposing the metal line; and forming a metal via in the first recess and electrically coupled to the metal line.

公开(公告)号：US11588030B2

公开(公告)日：2023-02-21

申请号：US17191278

申请日：2021-03-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tze-Liang Lee

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/78

Abstract: A method includes forming a gate structure over a substrate. A dielectric cap is formed over the gate structure. A source/drain contact is formed over a source/drain region over the substrate. An etch stop layer is selectively formed over the dielectric cap such that the etch stop layer expose the source/drain contact. An interlayer dielectric is formed over the etch stop layer and the source/drain contact. A source/drain via is formed in the ILD and is connected to the source/drain contact.

公开(公告)号：US20230050514A1

公开(公告)日：2023-02-16

申请号：US17399262

申请日：2021-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Kai Chen ,  Jei Ming Chen ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L21/311

Abstract: A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.

公开(公告)号：US20220406647A1

公开(公告)日：2022-12-22

申请号：US17480201

申请日：2021-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia Cheng Chou ,  Chung-Chi Ko ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532

Abstract: A structure includes a first conductive feature, a first etch stop layer over the first conductive feature, a dielectric layer over the first etch stop layer, and a second conductive feature in the dielectric layer and the first etch stop layer. The second conductive feature is over and contacting the first conductive feature. An air spacer encircles the second conductive feature, and sidewalls of the second conductive feature are exposed to the air spacer. A protection ring further encircles the second conductive feature, and the protection ring fully separates the second conductive feature from the air spacer.

公开(公告)号：US11502196B2

公开(公告)日：2022-11-15

申请号：US16933622

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Han-Chi Lin ,  Chunyao Wang ,  Ching Yu Huang ,  Tze-Liang Lee ,  Yung-Chih Wang

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/3065 ,  H01L27/088 ,  H01L21/8234

Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

公开(公告)号：US20220336202A1

公开(公告)日：2022-10-20

申请号：US17809917

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Wei-Che Hsieh ,  Ching Yu Huang ,  Hsin-Hao Yeh ,  Chunyao Wang ,  Tze-Liang Lee

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/033 ,  H01L21/308

Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.