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    Semiconductor memory device and testing method thereof
    51.
    发明授权
    Semiconductor memory device and testing method thereof 失效
    半导体存储器件及其测试方法

    公开(公告)号：US07567476B2

    公开(公告)日：2009-07-28

    申请号：US11392583

    申请日：2006-03-30

    Applicant: Toru Ishikawa

    Inventor： Toru Ishikawa

    IPC: G11C7/00

    CPC classification number: G11C29/32 ,  G11C29/1201 ,  G11C29/26 ,  G11C2029/3202

    Abstract: A semiconductor memory device includes mini arrays and a serial-parallel conversion circuit. The serial-parallel conversion circuit simultaneously writes two continuous data into mutually different mini arrays out of plural data that are continuously input synchronously with an internal clock, and continuously outputs two data simultaneously read from different mini arrays, synchronously with the internal clock. In testing the semiconductor memory device according to the present invention, one data is written during a period when an external clock having a cycle of an integer times cycle of the internal clock is fixed to a high level or a low level. With this arrangement, continuous data can be assigned to mutually different mini arrays.

    Abstract translation: 半导体存储器件包括微型阵列和串并联转换电路。 串行并行转换电路同时将两个连续数据写入与内部时钟同步连续输入的多个数据中的相互不同的微型阵列，并且与内部时钟同步地连续地输出与不同的迷你阵列同时读取的两个数据。 在根据本发明的半导体存储器件的测试中，在具有内部时钟周期的周期的外部时钟固定为高电平或低电平的期间，写入一个数据。 通过这种布置，可以将连续数据分配给相互不同的迷你阵列。

    PLL CIRCUIT FOR INCREASING POTENTIAL DIFFERENCE BETWEEN GROUND VOLTAGE AND REFERENCE VOLTAGE OR POWER SOURCE VOLTAGE OF OSCILLATION CIRCUIT
    52.
    发明申请
    PLL CIRCUIT FOR INCREASING POTENTIAL DIFFERENCE BETWEEN GROUND VOLTAGE AND REFERENCE VOLTAGE OR POWER SOURCE VOLTAGE OF OSCILLATION CIRCUIT 有权
    用于增加接地电压与参考电压或振荡电路的电源电压之间的潜在差异的PLL电路

    公开(公告)号：US20080291770A1

    公开(公告)日：2008-11-27

    申请号：US12033657

    申请日：2008-02-19

    Applicant: Toru Ishikawa

    Inventor： Toru Ishikawa

    IPC: H03L7/06 ,  G11C8/18

    CPC classification number: H03L7/0895 ,  H03L7/099 ,  H03L7/0995 ,  H03L2207/06

    Abstract: A PLL circuit includes a phase comparator for outputting a frequency control signal based on a result of comparison between phases of an input reference clock signal and a fed-back oscillation signal; an oscillation circuit, connected to the phase comparator, for outputting an oscillation signal having a frequency in accordance with the frequency control signal, a power source voltage, and a predetermined reference voltage; and a bias control circuit, connected to the oscillation circuit, for increasing either the potential difference between the reference voltage of the oscillation circuit and a ground voltage or the potential difference between the power source voltage of the oscillation circuit and the ground voltage. A transistor in the oscillation circuit can operate in a saturation area, thereby operating the PLL circuit at a high speed with a low power source voltage, without being easily affected by a variation in the temperature or other process conditions.

    Abstract translation: PLL电路包括：相位比较器，用于基于输入参考时钟信号和反馈振荡信号的相位之间的比较结果输出频率控制信号; 连接到所述相位比较器的振荡电路，用于输出具有与所述频率控制信号相对应的频率的振荡信号，电源电压和预定参考电压; 以及连接到振荡电路的偏置控制电路，用于增加振荡电路的参考电压与接地电压之间的电位差或振荡电路的电源电压与接地电压之间的电位差。 振荡电路中的晶体管可以在饱和区域中工作，从而以较低的电源电压高速运行PLL电路，而不会受到温度变化或其他工艺条件的影响。

    Semiconductor memory device
    53.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07251180B2

    公开(公告)日：2007-07-31

    申请号：US11365857

    申请日：2006-03-02

    Applicant: Toru Ishikawa

    Inventor： Toru Ishikawa

    IPC: G11C7/00

    CPC classification number: G11C11/406 ,  G11C2211/4061

    Abstract: An apparatus a counter, storage units for storing count values interrupted by a row address whose refresh period is subject to change; comparator circuits for comparing the counter outputs and the contents of the storage units to each other as to whether or not the counter outputs coincide with the contents of the storage units; a holding circuit for setting an output hit signal to an active state when a coincidence signal is output from the comparator circuits and for resetting the hit signal to an inactive state in the next following clock cycle; a circuit performing control for not propagating a refresh clock signal to the counter when the hit signal is in an active state and for propagating the refresh clock signal to the counter when the hit signal is in an inactive state; a circuit for replacing an output of the counter by a row address which changes part of the counter output when the hit signal is in an activate state to replace the counter output with the row address whose refresh period is subject to change to output the row address whose refresh period is subject to change as a refresh address.

    Abstract translation: 一种计数器装置，用于存储由刷新周期变化的行地址中断的计数值的存储单元; 比较电路，用于将计数器输出和存储单元的内容彼此比较，以便计数器输出是否与存储单元的内容一致; 保持电路，用于当从比较器电路输出一致信号时将输出命中信号设置为有效状态，并在下一个后续时钟周期将命中信号复位为无效状态; 执行控制，用于当所述命中信号处于活动状态时不向所述计数器传播刷新时钟信号，并且当所述命中信号处于非活动状态时将所述刷新时钟信号传播到所述计数器; 一个电路，用于当命中信号处于激活状态时改变计数器输出的一部分的行地址替换计数器的输出，以用刷新周期改变的行地址替换计数器输出以输出行地址 刷新周期可能会随刷新地址而变化。

    Semiconductor memory device and testing method thereof
    55.
    发明申请
    Semiconductor memory device and testing method thereof 失效

    公开(公告)号：US20060233035A1

    公开(公告)日：2006-10-19

    申请号：US11392583

    申请日：2006-03-30

    Applicant: Toru Ishikawa

    Inventor： Toru Ishikawa

    IPC: G11C7/00

    CPC classification number: G11C29/32 ,  G11C29/1201 ,  G11C29/26 ,  G11C2029/3202

    Abstract: A semiconductor memory device includes mini arrays and a serial-parallel conversion circuit. The serial-parallel conversion circuit simultaneously writes two continuous data into mutually different mini arrays out of plural data that are continuously input synchronously with an internal clock, and continuously outputs two data simultaneously read from different mini arrays, synchronously with the internal clock. In testing the semiconductor memory device according to the present invention, one data is written during a period when an external clock having a cycle of an integer times cycle of the internal clock is fixed to a high level or a low level. With this arrangement, continuous data can be assigned to mutually different mini arrays.

    Fuel injection method of internal combustion engine, fuel injection valve of the same, and internal combustion engine
    56.
    发明授权
    Fuel injection method of internal combustion engine, fuel injection valve of the same, and internal combustion engine 失效
    内燃机燃油喷射方式，燃油喷射阀及内燃机

    公开(公告)号：US07082922B2

    公开(公告)日：2006-08-01

    申请号：US10962753

    申请日：2004-10-13

    Applicant: Motoyuki Abe ,  Noriyuki Maekawa ,  Takuya Shiraishi ,  Hiroshi Fujii ,  Mamoru Fujieda ,  Toru Ishikawa ,  Yoshiyuki Tanabe

    Inventor： Motoyuki Abe ,  Noriyuki Maekawa ,  Takuya Shiraishi ,  Hiroshi Fujii ,  Mamoru Fujieda ,  Toru Ishikawa ,  Yoshiyuki Tanabe

    IPC: F02B15/00

    CPC classification number: F02M61/1806 ,  F02M61/14 ,  F02M61/162 ,  F02M69/045

    Abstract: In order to provide a fuel injection method of an internal combustion engine having higher combustion stability which can direct a part of concentrated fuel spray toward an ignition plug according to a fuel injection atmosphere, a fuel injection valve thereof, and an internal combustion engine, the present invention provides a fuel injection method of an internal combustion engine for injecting fuel so as to generate a part of high spray concentration and a part of low spray concentration on the cross section of spray by giving swirling force to fuel from an injection hole at the front end of a fuel injection valve, comprising the step of setting a reference indicating the position of a axis of the fuel injection valve indicating the injection direction of the part of high spray concentration in the rotational direction when fuel is injected into an atmosphere under the atmospheric pressure.

    Abstract translation: 为了提供具有较高燃烧稳定性的内燃机的燃料喷射方法，其能够根据燃料喷射气体，其燃料喷射阀和内燃机将一部分浓缩燃料喷射引向火花塞， 本发明提供了一种用于喷射燃料的内燃机的燃料喷射方法，以便在喷雾截面上产生一部分高喷雾浓度和一部分低喷雾浓度，该喷射浓度和一部分喷雾浓度通过从喷射孔中的喷射孔向燃料施加旋动力 燃料喷射阀的前端包括以下步骤：当燃料喷射到下面的气氛中时，将指示燃料喷射阀的轴的位置的参考指示指示喷射高浓度部分的喷射方向的部分在旋转方向上的步骤 气压。

    Delay producing method, delay adjusting method based on the same, and delay producing circuit and delay adjusting circuit applied with them
    57.
    发明授权
    Delay producing method, delay adjusting method based on the same, and delay producing circuit and delay adjusting circuit applied with them 失效
    延迟产生方法，延迟调整方法及其应用延迟产生电路和延迟调整电路

    公开(公告)号：US06937081B2

    公开(公告)日：2005-08-30

    申请号：US10714768

    申请日：2003-11-17

    Applicant: Toru Ishikawa

    Inventor： Toru Ishikawa

    IPC: G06F1/10 ,  G11C11/4076 ,  H03H7/30 ,  H03H11/26 ,  H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H03K5/153 ,  H03L7/00 ,  H03L7/081

    CPC classification number: H03L7/0814 ,  H03K5/133 ,  H03K2005/00156

    Abstract: A delay adjusting circuit that can minimize a delay at selectors even when the number of delay stages and the number of selector stages are increased, to enable a stable and speedy operation. As selectors S in a delay producing circuit (11), 2:1 selectors, each of the type that selectively outputs one from two inputs, may be used which are connected to input/output portions of N-stage delay elements D1 to DN for enabling delayed output of an even-stage delayed clock signal (Even) and an odd-stage delayed clock signal (Odd). In this case, the 2:1 selectors are arranged in a two-stage configuration including the for-even-stage selectors (S1, S3, . . . , Sn, S(n+2)) and the for-odd-stage selectors (S2, . . . , S(n+1), S(n+3)). The even-stage delayed clock signal (Even) is obtained through the first-stage selector S1. The odd-stage delayed clock signal (Odd) is obtained through the second-stage selector S2.

    Abstract translation: 延迟调整电路即使当延迟级数和选择器级数增加时，也可以使选择器的延迟最小化，以实现稳定且快速的操作。 作为延迟产生电路（11）中的选择器S，可以使用2：1个选择器，每个选择器从两个输入中选择性地输出一个，其连接到N级延迟元件D 1至DN的输入/输出部分 用于使得能够延迟输出偶数级延迟时钟信号（偶数）和奇数级延迟时钟信号（Odd）。 在这种情况下，2：1选择器被布置成包括平均级选择器（S 1，S 3，...，Sn，S（n + 2））和奇数 阶段选择器（S 2，...，S（n + 1），S（n + 3））。 通过第一级选择器S1获得偶数级延迟时钟信号（偶数）。 通过第二级选择器S2获得奇数级延迟时钟信号（Odd）。

    Fuel injection valve and its apparatus, method for manufacturing internal combustion engine and fuel injection valve and its nozzle body, and method for manufacturing the same
    58.
    发明授权
    Fuel injection valve and its apparatus, method for manufacturing internal combustion engine and fuel injection valve and its nozzle body, and method for manufacturing the same 失效
    燃油喷射阀及其装置，内燃机和燃料喷射阀及其喷嘴体的制造方法及其制造方法

    公开(公告)号：US06845748B2

    公开(公告)日：2005-01-25

    申请号：US10329439

    申请日：2002-12-27

    Applicant: Masayuki Kobayashi ,  Koji Harada ,  Toru Ishikawa

    Inventor： Masayuki Kobayashi ,  Koji Harada ,  Toru Ishikawa

    IPC: F02M61/04 ,  F02M51/06 ,  F02M61/16 ,  F02M61/18 ,  F02M63/00 ,  F02M69/04 ,  F02M51/00

    CPC classification number: F02M61/188 ,  F02M51/0671 ,  F02M61/162 ,  F02M61/168 ,  F02M61/18 ,  F02M69/045 ,  F02M2200/505

    Abstract: It is an object of the present invention is to provide a fuel injection valve and its apparatus, and an internal combustion engine, a method for manufacturing the fuel injection valve and its nozzle body, and a method for manufacturing the same capable of securing highly accurate and stabilized fuel spraying characteristics. The fuel injection valve comprises a nozzle body, an injection hole provided in the nozzle body, a valve body for opening and closing a fuel passage from the injection hole relative to the nozzle body, and a drive means for driving the valve body, wherein formed is a protrusion having an opening in communication with the downstream side of the injection hole of the nozzle body and which part of the side and an extreme end are opened. The invention resides in a nozzle body and manufacturing it by plastic processing, and an internal combustion engine using the same.

    Abstract translation: 本发明的一个目的是提供一种燃料喷射阀及其装置和一种内燃机，用于制造燃料喷射阀及其喷嘴体的方法及其制造方法，其能够确保高精度 并具有稳定的燃油喷射特性。 燃料喷射阀包括喷嘴体，设置在喷嘴体中的喷射孔，用于从喷射孔相对于喷嘴体打开和关闭燃料通道的阀体以及用于驱动阀体的驱动装置，其中形成 是具有与喷嘴体的喷射孔的下游侧连通并且侧面的一部分和末端被打开的开口的突起。 本发明涉及一种喷嘴体并通过塑性加工制造，以及使用其的内燃机。

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