公开(公告)号：US08643189B1

公开(公告)日：2014-02-04

申请号：US13550627

申请日：2012-07-17

申请人： Boon Yew Low ,  Navas Khan Oratti Kalandar ,  Lan Chu Tan

发明人： Boon Yew Low ,  Navas Khan Oratti Kalandar ,  Lan Chu Tan

IPC分类号： H01L23/12 ,  H01L23/58 ,  H01L23/50 ,  H01L23/34

CPC分类号： H01L24/49 ,  H01L23/3121 ,  H01L23/49531 ,  H01L23/49827 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A packaged semiconductor die has a die support mounting surface mounted to a die support having external connectors. A die connection pad surface opposite to die supporting mount surface has associated die connection pads that are circuit nodes of the semiconductor die. The die connection pad surface also has a power rail pad. The power rail pad has a surface area larger than surface areas of the die connection pads. Bond wires electrically couple the power rail pad to two or more of the die connection pads.

摘要翻译： 封装的半导体管芯具有安装到具有外部连接器的管芯支撑件的管芯支撑安装表面。 与管芯支撑安装表面相对的管芯连接焊盘表面具有作为半导体管芯的电路节点的相关联的管芯连接焊盘。 管芯连接焊盘表面还具有电源轨焊盘。 电源轨焊盘的表面积大于管芯连接焊盘的表面积。 接合线将电源轨焊盘电耦合到两个或更多个管芯连接焊盘。

公开(公告)号：US08378435B2

公开(公告)日：2013-02-19

申请号：US12960571

申请日：2010-12-06

申请人： Wai Yew Lo ,  Lan Chu Tan

发明人： Wai Yew Lo ,  Lan Chu Tan

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： H01L24/97 ,  G01L19/0069 ,  G01L19/147 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method of packaging a pressure sensing die includes providing a lead frame with lead fingers and attaching the pressure sensing die to the lead fingers such that bond pads of the die are electrically coupled to the lead fingers and a void is formed between the die and the lead fingers. A gel material is dispensed via an underside of the lead frame into the void such that the gel material substantially fills the void. The gel material is then cured and the die and the lead frame are encapsulated with a mold compound. The finished package does not include a metal lid.

摘要翻译： 一种包装压力传感管芯的方法包括提供具有引线指状物的引线框架并将压力感测裸片连接到引线指，使得管芯的接合焊盘电连接到引线指，并且在管芯和管芯之间形成空隙 铅笔指 凝胶材料通过引线框架的下侧分配到空隙中，使得凝胶材料基本上填充空隙。 然后将凝胶材料固化，并将模具和引线框架用模具化合物包封。 成品包装不包括金属盖。

公开(公告)号：US20080182120A1

公开(公告)日：2008-07-31

申请号：US11627980

申请日：2007-01-28

申请人： Lan Chu Tan ,  Heng Keong Yip ,  Cheng Choi Yong

发明人： Lan Chu Tan ,  Heng Keong Yip ,  Cheng Choi Yong

IPC分类号： B32B3/00

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/48091 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/05042 ,  Y10T428/1241 ,  H01L2224/45099

摘要： A bond pad (12, 14) for a semiconductor device (10) is generally L-shaped and includes a first portion (20, 24) for receiving a bond wire, and a second portion (22, 26) extending substantially perpendicularly from the first portion (20, 24). The bond pad (12) may include a third portion (16, 18) adjacent to the first portion (20). The third portion (16, 18) may be an embedded power pad (16) or an embedded ground pad (18).

摘要翻译： 用于半导体器件（10）的接合焊盘（12,14）通常为L形并且包括用于接收接合线的第一部分（20,24）和从所述第二部分延伸的第二部分（22,26） 第一部分（20,24）。 接合焊盘（12）可以包括与第一部分（20）相邻的第三部分（16,18）。 第三部分（16,18）可以是嵌入式功率垫（16）或嵌入式接地垫（18）。

公开(公告)号：US20080179710A1

公开(公告)日：2008-07-31

申请号：US11668453

申请日：2007-01-29

申请人： Heng Keong Yip ,  Wai Yew Lo ,  Lan Chu Tan

发明人： Heng Keong Yip ,  Wai Yew Lo ,  Lan Chu Tan

IPC分类号： H01L23/544 ,  H01L21/76

CPC分类号： H01L21/3043 ,  H01L21/02118 ,  H01L21/312 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing tool within each path, a pair of spaced apart lines is fabricated. Each line defines a dicing edge of a respective path and has at least one trench extending between a top surface of the wafer and the substrate. Each trench is filled with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.

摘要翻译： 制造用于切割的半导体晶片的方法包括在基板上提供包括基板和多个上层的半导体晶片，形成管芯区域的形成。 该组合被布置成使得相邻的模具区域被用于每个路径内的切割工具的路径分开，制造一对间隔开的线。 每条线限定相应路径的切割边缘，并且具有在晶片的顶表面和基底之间延伸的至少一个沟槽。 每个沟槽填充有应力吸收材料，用于在切割期间减少模具区域上的模具工具引起的应力。

公开(公告)号：US06693020B2

公开(公告)日：2004-02-17

申请号：US09803749

申请日：2001-03-12

申请人： Kok Wai Mui ,  Fuaida Bte Harun ,  Lan Chu Tan ,  Mohd Faizairi Bin Mohd Nor

发明人： Kok Wai Mui ,  Fuaida Bte Harun ,  Lan Chu Tan ,  Mohd Faizairi Bin Mohd Nor

IPC分类号： H01L21322

CPC分类号： H01L24/05 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/32134 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/0381 ,  H01L2224/04042 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/48847 ,  H01L2224/73265 ,  H01L2224/85011 ,  H01L2224/85013 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  Y10S438/905 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/03

摘要： A method of preparing a semiconductor wafer having a integrated circuits formed on it that have pads formed of copper includes the steps of removing oxide from the copper pads and then the vacuum packing the wafer in a shock-proof container. The oxide may be removed from the copper pads in a number of ways. A first way includes cleaning the wafer in an alkaline solution, performing acid neutralization on the cleaned wafer, and then drying the wafer. A second way includes cleaning the wafer with an acid solution, rinsing the acid cleaned wafer with water, applying an anti-oxidant activator to the surface of the copper pads, rinsing the wafer with water after the application of the anti-oxidant activator, and then drying the water rinsed wafer. Yet a third way includes plasma cleaning the copper pads using a combination of about 5-10% Hydrogen and about 90-95% Argon and then sputtering a very thin layer of aluminum on a surface of the copper pads. The layer of aluminum has a thickness of about 1-5 nanometers.

摘要翻译： 制备具有形成在其上的具有由铜形成的焊盘的集成电路的半导体晶片的方法包括以下步骤：从铜焊盘去除氧化物，然后将晶片真空包装在防震容器中。 可以以多种方式从铜焊盘去除氧化物。 第一种方法包括在碱性溶液中清洗晶片，在清洁的晶片上进行酸中和，然后干燥晶片。 第二种方法包括用酸溶液清洗晶片，用水冲洗酸洗的晶片，将抗氧化剂活化剂施加到铜垫的表面，在施用抗氧化剂活化剂之后用水冲洗晶片;以及 然后干燥水冲洗的晶片。 第三种方法包括使用约5-10％氢气和约90-95％氩气的组合对铜焊盘进行等离子体清洗，然后在铜焊盘的表面上溅射非常薄的铝层。 铝层的厚度约为1-5纳米。