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51.发明申请公开(公告)号：US20170177482A1
公开(公告)日：2017-06-22
申请号：US14975487
申请日：2015-12-18
申请人： Intel Corporation
发明人： Daniel GREENSPAN
CPC分类号： G06F12/0815 , G06F3/0602 , G06F3/0659 , G06F3/0685 , G06F9/4406 , G06F12/0891 , G06F2212/1021 , G06F2212/60 , G06F2212/621
摘要： An apparatus is described that includes a memory controller to interface to a multi-level system memory having a higher level and a lower level. The memory controller includes register space to indicate first and second modes of operation. In the first mode of operation the higher level is available and the lower level is unavailable. In the second mode of operation the higher level is available and the lower level is available.
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公开(公告)号：US20170153851A1
公开(公告)日：2017-06-01
申请号：US15226855
申请日：2016-08-02
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0602 , G06F3/0613 , G06F3/0619 , G06F3/064 , G06F3/065 , G06F3/067 , G06F3/0683 , G06F3/0689 , G06F11/1451 , G06F11/1464 , G06F11/1469 , G06F11/201 , G06F2201/805 , G06F2201/815
摘要： Provided are a computer program product, system, and method for data unit classification in accordance with one embodiment of the present description, in which in response to a data processing command, a storage controller classifies data units of a storage unit as either allocated to a data set or as unallocated to any data set. If allocated to a data set, the storage controller can further classify data set-allocated data units as either containing client data or metadata or as empty. In accordance with one aspect of the present description, the storage controller may bypass data processing of the data units which have not been allocated to any data set or otherwise do not contain client data or metadata. Other aspects of data unit classification in accordance with the present description are described.
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公开(公告)号：US20170108902A1
公开(公告)日：2017-04-20
申请号：US14986930
申请日：2016-01-04
发明人： Nikhil HEDGE , Bruce MEALEY , Mark D. ROGERS
CPC分类号： G06F1/24 , G06F3/0602 , G06F3/0608 , G06F3/0629 , G06F3/0644 , G06F3/0652 , G06F3/067 , G06F3/0673 , G06F9/5016 , G06F12/0223 , G06F12/023 , G06F12/1009 , G06F2009/45583 , G06F2212/1044 , G06F2212/2542
摘要： Embodiments disclosed herein generally relate to techniques for zeroing memory in computing systems where access to memory is non-uniform. One embodiment provides a method. The method generally includes receiving, via a system call, a request for a pool of memory. The method also includes determining a size of the requested pool of memory, and creating a dummy memory segment. The size of the dummy memory segment is larger than the size of the requested pool of memory. The method further includes filling the dummy memory segment with one or more pages, based on the determined size of the requested pool of memory, and deleting the dummy memory segment.
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公开(公告)号：US20170075592A1
公开(公告)日：2017-03-16
申请号：US15343861
申请日：2016-11-04
发明人： JOHN K. DEBROSSE , BLAKE G. FITCH , MICHELE M. FRANCESCHINI , TODD E. TAKKEN , DANIEL C. WORLEDGE
CPC分类号： G06F3/0613 , G06F3/0602 , G06F3/061 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G06F3/0679 , G06F3/0688 , G06F13/1668 , G11C7/10 , G11C7/1003 , G11C7/1015 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069
摘要： A method for memory management includes streaming bits to a memory buffer on a memory device using a write data channel that optimizes a speed of writing to the memory devices. The bits are written to non-volatile memory cells in the memory device at a first speed, using a bi-directional bus. Bits are read from the memory device over a read channel to provide reads at a second speed that is slower than the first speed, using the bi-directional bus.
摘要翻译： 一种用于存储器管理的方法包括使用优化对存储器件的写入速度的写数据通道的存储器设备中的存储器缓冲器的流比特流。 这些位使用双向总线以第一速度写入存储器件中的非易失性存储器单元。 通过读通道从存储器件读取位，以使用双向总线提供比第一速度慢的第二速度的读取。
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公开(公告)号：US09569109B2
公开(公告)日：2017-02-14
申请号：US14747976
申请日：2015-06-23
发明人： John K. Debrosse , Blake G. Fitch , Michele M. Franceschini , Todd E. Takken , Daniel C. Worledge
CPC分类号： G06F3/0613 , G06F3/0602 , G06F3/061 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G06F3/0679 , G06F3/0688 , G06F13/1668 , G11C7/10 , G11C7/1003 , G11C7/1015 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069
摘要： A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.
摘要翻译： 存储器包括非易失性存储器件，每个存储器件具有多个非易失性存储器单元。 写控制器使用具有写总线驱动器，接收器和写总线拓扑的写数据通道以N组的方式将比特流分组到存储器件，其利用高速信令优化对存储器件的写入速度。 连续的比特组被写入相应的存储器件中的连续的存储器单元。 自参考读取控制器使用具有读驱动器，接收器和读总线拓扑的读通道从存储器件读取位，其中不包括高速或低延迟数据传输的设计要求。
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56.发明申请AFFINITY-AWARE PARALLEL ZEROING OF MEMORY FOR INITIALIZATION OF LARGE PAGES IN NON-UNIFORM MEMORY ACCESS (NUMA) SERVERS 有权对非均匀存储器访问（NUMA）服务器中的大型页面进行初始化的存储空间的平均值并行调整公开(公告)号：US20160378388A1
公开(公告)日：2016-12-29
申请号：US14883304
申请日：2015-10-14
发明人： Nakhil HEGDE , Bruce MEALEY , Mark D. ROGERS
IPC分类号： G06F3/06
CPC分类号： G06F1/24 , G06F3/0602 , G06F3/0608 , G06F3/0629 , G06F3/0644 , G06F3/0652 , G06F3/067 , G06F3/0673 , G06F9/5016 , G06F12/0223 , G06F12/023 , G06F12/1009 , G06F2009/45583 , G06F2212/1044 , G06F2212/2542
摘要： Embodiments disclosed herein generally relate to techniques for zeroing memory in computing systems where access to memory is non-uniform. Embodiments include a system having a processor and a memory storing a program; and other embodiments include a computer readable medium containing a program. When executed on a processor, the program causes the processor to perform an operation that includes receiving, via a system call, a request for a pool of memory. The operation also includes determining a size of the requested pool of memory, and creating a dummy memory segment. The size of the dummy memory segment is larger than the size of the requested pool of memory. The operation further includes filling the dummy memory segment with one or more pages, based on the determined size of the requested pool of memory, and deleting the dummy memory segment.
摘要翻译： 本文公开的实施例通常涉及用于对存储器访问不均匀的计算系统中的存储器归零的技术。 实施例包括具有处理器和存储程序的存储器的系统; 并且其他实施例包括包含程序的计算机可读介质。 当在处理器上执行时，程序使处理器执行包括经由系统调用接收对存储器池的请求的操作。 该操作还包括确定所请求的存储池的大小，以及创建虚拟存储器段。 虚拟内存段的大小大于请求的内存池的大小。 该操作还包括基于确定的所请求的存储池的大小填充虚拟存储器段与一个或多个页面，以及删除虚拟存储器段。
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公开(公告)号：US20160283116A1
公开(公告)日：2016-09-29
申请号：US14671968
申请日：2015-03-27
申请人： INTEL CORPORATION
发明人： Anand S. RAMALINGAM
CPC分类号： G06F3/0602 , G06F3/0611 , G06F3/0629 , G06F3/0656 , G06F3/0679 , G06F3/0683 , G06F12/0895 , G06F13/16 , G06F2212/202 , G06F2212/60
摘要： In one embodiment, sequential write stream management is employed to improve the sequential nature of write data placed in a storage such as a solid state drive, notwithstanding intermingling of write commands from various sequential and nonsequential streams from multiple processor nodes in a system. In one embodiment, write data from an identified sequential write stream is placed in a storage area assigned to that particular identified sequential write stream. In another aspect, detected sequential write streams are identified as a function of write velocity of the detected stream. Other aspects are described herein.
摘要翻译： 在一个实施例中，尽管来自系统中来自多个处理器节点的各种顺序和非顺序流的写入命令的混合，采用顺序写入流管理来改善放置在诸如固态驱动器的存储器中的写入数据的顺序特性。 在一个实施例中，将从所识别的顺序写入流写入数据放置在分配给该特定识别顺序写入流的存储区域中。 在另一方面，检测到的顺序写入流被识别为检测到的流的写入速度的函数。 本文描述了其它方面。
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公开(公告)号：US09430162B1
公开(公告)日：2016-08-30
申请号：US14956329
申请日：2015-12-01
CPC分类号： G06F3/0659 , G06F3/0602 , G06F3/0613 , G06F3/0619 , G06F3/064 , G06F3/065 , G06F3/067 , G06F3/0683 , G06F3/0689 , G06F11/1451 , G06F11/1464 , G06F11/1469 , G06F11/201 , G06F2201/805 , G06F2201/815
摘要： Provided are a computer program product, system, and method for data unit classification in accordance with one embodiment of the present description, in which in response to a data processing command, a storage controller classifies data units of a storage unit as either allocated to a data set or as unallocated to any data set. If allocated to a data set, the storage controller can further classify data set-allocated data units as either containing client data or metadata or as empty. In accordance with one aspect of the present description, the storage controller may bypass data processing of the data units which have not been allocated to any data set or otherwise do not contain client data or metadata. Other aspects of data unit classification in accordance with the present description are described.
摘要翻译： 提供了根据本说明书的一个实施例的用于数据单元分类的计算机程序产品，系统和方法，其中响应于数据处理命令，存储控制器将存储单元的数据单元分配为分配给 数据集或未分配给任何数据集。 如果分配给数据集，则存储控制器可以将数据集分配的数据单元进一步分类为包含客户端数据或元数据或为空。 根据本说明书的一个方面，存储控制器可以旁路未被分配给任何数据集的数据单元的数据处理，否则不包含客户端数据或元数据。 描述根据本说明书的数据单元分类的其他方面。
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公开(公告)号：US09244824B2
公开(公告)日：2016-01-26
申请号：US13932352
申请日：2013-07-01
发明人： Sun-Young Lim , Dong-Hwi Kim
CPC分类号： G06F12/00 , G06F3/0602 , G06F3/0604 , G06F12/0238 , G06F13/1684 , G06F13/382 , Y02D10/14 , Y02D10/151
摘要： A memory sub-system includes a main memory, a storage device, a control unit, and a common interface unit. The control unit is configured to control the main memory and the storage device. The common interface unit is operatively coupled to the control unit, and is configured to access the main memory and the storage device through the control unit in response to a request received from a host.
摘要翻译： 存储器子系统包括主存储器，存储装置，控制单元和公共接口单元。 控制单元被配置为控制主存储器和存储设备。 公共接口单元可操作地耦合到控制单元，并且被配置为响应于从主机接收到的请求，通过控制单元访问主存储器和存储设备。
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公开(公告)号：US09218284B2
公开(公告)日：2015-12-22
申请号：US14149733
申请日：2014-01-07
发明人： Tony Yoon , Akio Goto , Chi Kong Lee , Masayuki Urabe
CPC分类号： G06F12/0246 , G06F3/0601 , G06F3/0602 , G06F3/0604 , G06F3/0605 , G06F3/061 , G06F3/0622 , G06F3/0628 , G06F3/0653 , G06F3/0659 , G06F13/1689
摘要： In some implementations, an apparatus includes a first programmable hardware timer that specifies an initial wait time before issuing two or more commands to a storage device, and a second programmable hardware timer that specifies an interval time between at least two commands of the two or more commands.
摘要翻译： 在一些实现中，一种装置包括：第一可编程硬件定时器，其在向存储设备发出两个或多个命令之前指定初始等待时间;以及第二可编程硬件定时器，其指定两个或更多个命令之间的间隔时间 命令。
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