公开(公告)号：US11973153B2

公开(公告)日：2024-04-30

申请号：US17445371

申请日：2021-08-18

Applicant: Rambus Inc.

Inventor： Yohan Frans ,  Simon Li ,  John Eric Linstadt ,  Jun Kim

IPC: H01L31/0236 ,  G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F13/16 ,  G06F13/372

CPC classification number: H01L31/02366 ,  G06F3/0613 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1684 ,  G06F13/372 ,  G06F12/00 ,  G06F13/16 ,  Y02D10/00

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

公开(公告)号：US11972111B2

公开(公告)日：2024-04-30

申请号：US18052350

申请日：2022-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyong Park ,  Minseok Kim ,  Jisu Kim ,  Ilhan Park ,  Doohyun Kim

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0629 ,  G06F3/0679

Abstract: A memory device for improving the speed of a program operation and an operating method thereof is provided. The memory device includes a memory cell array including a plurality of memory cells, a voltage generator configured to generate voltages for one or more program operations and a verify operation performed on the plurality of memory cells, a control logic configured to perform a control operation on the plurality of memory cells so that a first program and a second program loop are performed, a second program operation being performed based on a compensation voltage level determined based on a result of the first verify operation, and a plurality of bit lines connected to the memory cell array, wherein the first verify operation includes first even sensing and second even sensing on even-numbered bit lines, and first odd sensing and second odd sensing on odd-numbered bit lines.

公开(公告)号：US11972109B2

公开(公告)日：2024-04-30

申请号：US17283495

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Hua Tan ,  Lingye Zhou

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0673

Abstract: Methods, systems, and devices for two-stage buffer operations supporting write commands are described. If data is written to a memory device starting at a multi-plane page offset other than zero, the read performance for the data may decrease significantly due to die misalignment. To avoid die misalignment, a memory system may support two buffers for write data: a flush buffer and a temporary buffer. The memory system may determine whether to add received data to the flush buffer, the temporary buffer, or a combination thereof based on a data transfer size and a threshold size. If the data in the temporary buffer satisfies a copy condition, the data in the temporary buffer is copied into the flush buffer. If the data in the flush buffer satisfies a flush condition, the data in the flush buffer is written to the memory device starting at a multi-plane page offset of zero.

公开(公告)号：US20240126444A1

公开(公告)日：2024-04-18

申请号：US18180382

申请日：2023-03-08

Applicant: SK hynix Inc.

Inventor： Tae Young AHN

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: A method is provided in which a core processor located adjacent to a memory and processing data of the memory in a proximity data processing scheme reads and processes the data of the memory by simultaneously using a plurality of channels used by the memory. Since data processing is performed simultaneously using a total bandwidth between the memory and the core processor, the efficiency of the proximity data processing scheme by the core processor may be improved.

公开(公告)号：US11960412B2

公开(公告)日：2024-04-16

申请号：US18047982

申请日：2022-10-19

Applicant: Unification Technologies LLC

Inventor： David Flynn ,  Jonathan Thatcher ,  Michael Zappe

IPC: G06F3/06 ,  G06F1/18 ,  G06F9/52 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/12 ,  G06F12/121 ,  G06F12/123 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42 ,  H04L67/02 ,  H05K7/14 ,  H04L67/1097

CPC classification number: G06F12/121 ,  G06F1/183 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0643 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F3/0688 ,  G06F9/52 ,  G06F9/54 ,  G06F11/108 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/12 ,  G06F12/123 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/426 ,  H04L67/02 ,  H05K7/1444 ,  H05K7/1487 ,  G06F2211/002 ,  G06F2211/103 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/222 ,  G06F2212/70 ,  G06F2212/7205 ,  H04L67/1097 ,  Y02D10/00

Abstract: A method for managing data in a NAND flash storage system is provided. The method includes one or more of receiving an empty data segment directive at a storage controller, returning a data string including data of a predetermined logic level in response to a read command requesting to read data associated with a logical identifier included in the empty data segment directive, maintaining an index of mapping between the logical identifier and a physical storage location, updating the index to indicate data at the physical storage location does not need to be preserved, monitoring one or more physical storage locations, including the physical storage location, to determine a percentage of the one or more physical storage locations that do not need to be preserved, and initiating garbage collection on the one or more physical storage locations in response to the percentage reaching a threshold. The empty data segment directive includes a logical identifier associated with the physical storage location.

公开(公告)号：US20240118809A1

公开(公告)日：2024-04-11

申请号：US18166591

申请日：2023-02-09

Applicant: SK hynix Inc.

Inventor： Ji Hoon SEOK

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0253

Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of memory cells. The controller is configured to select first map data entries associated with first data entries stored in a first region of the memory device that includes some of the plurality of memory cells, to exclude a second map data entry associated with second data entry sequentially read from among the first map data entries, and to transmit a remaining first map data entry to an external device.

公开(公告)号：US11954372B2

公开(公告)日：2024-04-09

申请号：US17964734

申请日：2022-10-12

Applicant: Nutanix, Inc.

Inventor： Kiran Tatiparthi ,  Mukul Sharma ,  Saibal Kumar Adhya ,  Sandeep Ashok Ghadage ,  Swapnil Ingle

IPC: G06F3/06

CPC classification number: G06F3/0665 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/067 ,  G06F3/0683

Abstract: A technique efficiently migrates a live virtual disk (vdisk) across storage containers of a cluster having a plurality of nodes deployed in a virtualization environment. Each node is embodied as a physical computer with hardware resources, such as processor, memory, network and storage resources, that are virtualized to provide support for one or more user virtual machines (UVM) executing on the node. The storage resources include storage devices embodied as a storage pool that is logically segmented into the storage containers configured to store one or more vdisks. The storage containers include a source container having associated storage policies and a destination container having different (new) storage policies. The technique enables migration of the live vdisk from the source container to the destination container without powering down the UVM and halting input/output accesses to the vdisk, and while maintaining uninterrupted servicing of data from the live vdisk during the migration transparent to the executing UVM.

公开(公告)号：US11947821B2

公开(公告)日：2024-04-02

申请号：US16901436

申请日：2020-06-15

Applicant: ALIBABA GROUP HOLDING LIMITED

Inventor： Yongbin Gu ,  Pengcheng Li ,  Tao Zhang ,  Yuan Xie

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0613 ,  G06F3/0673

Abstract: The present disclosure provides methods, systems, and non-transitory computer readable media for managing a primary storage unit of an accelerator. The methods include assessing activity of the accelerator; assigning, based on the assessed activity of the accelerator, a lease to a group of one or more pages of data on the primary storage unit, wherein the assigned lease indicates a lease duration; and marking, in response to the expiration of the lease duration indicated by the lease, the group of one or more pages of data as an eviction candidate.

公开(公告)号：US20240103733A1

公开(公告)日：2024-03-28

申请号：US18223558

申请日：2023-07-19

Applicant: Silicon Motion, Inc.

Inventor： Yu-Ta Chen

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0613 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/1009

Abstract: A data storage device includes a memory device and a memory controller. The memory controller uses a first predetermined memory block as a buffer to receive data from a host device. In response to a write command received from the host device, the memory controller determines a sub-region corresponding to the write command, determines whether the sub-region is a hot-write sub-region according to a write count corresponding to the sub-region and accordingly determines whether to use a second predetermined memory block as another buffer to receive data from the host device. When the memory controller determines that the sub-region corresponding to the write command is a hot-write sub-region, the memory controller writes the data into the second predetermined memory block. When the memory controller determines that the sub-region is not a hot-write sub-region, the memory controller writes the data into the first predetermined memory block.

公开(公告)号：US11934660B1

公开(公告)日：2024-03-19

申请号：US18503918

申请日：2023-11-07

Applicant: Qumulo, Inc.

Inventor： Matthew Christopher McMullan ,  Aaron James Passey ,  Jonathan Michael MacLaren ,  Yuxi Bai ,  Thomas Gregory Rothschilds ,  Michael Anthony Chmiel ,  Tyler Morrison Moody ,  Pathirat Kosakanchit ,  Rowan Arthur Phipps

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0607 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0683

Abstract: Embodiments are directed to tiered data store with persistent layers. A write tier in the file system for storing in a file system. A value for a performance metric that corresponds to write requests to the file system may be predicted based on characteristics of the write requests such that the performance metric may be determined based on a plurality of interactions with the write tier. The predicted value that exceeds a threshold value of the performance metric may be employed to cause performance of further actions, including: queuing a portion of the write requests in a memory buffer based on the predicted value and the threshold value; combining the queued portion of the write requests into s; storing the data segments in the write tier such that a measured value of the performance metric may be less than the threshold value.