公开(公告)号：US20180277744A1

公开(公告)日：2018-09-27

申请号：US15702403

申请日：2017-09-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Masaru TOKO ,  Keiji HOSOTANI ,  Hisanori AIKAWA ,  Tatsuya KISHI

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a first non-magnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the first magnetic layer and having a fixed magnetization direction and provided on the first magnetic layer. The second magnetic layer includes a non-magnetic metal including at least one of Mo (molybdenum), Ta (tantalum), W (tungsten), Hf (hafnium), Nb (niobium) and Ti (titanium).

公开(公告)号：US20180277183A1

公开(公告)日：2018-09-27

申请号：US15702430

申请日：2017-09-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiji HOSOTANI ,  Tatsuya KISHI ,  Akira KATAYAMA

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10

CPC classification number: G11C11/161 ,  G11C11/1673 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10

Abstract: According to one embodiment, a memory includes a first MTJ element having a first area along a first plane; and second MTJ elements each having a second area along the first plane. The second area is larger than or equal to twice the first area and smaller than or equal to five times the first area. Each of the second MTJ elements includes a first ferromagnet, a second ferromagnet, and a first nonmagnet. Respective magnetizations of respective first ferromagnets of the second MTJ elements are oriented along a first direction. Respective magnetizations of respective second ferromagnets of the second MTJ elements are oriented along a second direction. One of the second MTJ elements is coupled to another one of the second MTJ elements in series or in parallel.

公开(公告)号：US20180269255A1

公开(公告)日：2018-09-20

申请号：US15691469

申请日：2017-08-30

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuichi ITO

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L23/552 ,  H01L43/12

CPC classification number: H01L27/228 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  H01L23/552 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: According to one embodiment, a magnetic memory device includes a memory cell array unit including magnetoresistive elements provided in an array in first and second directions, each including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer between the first and second magnetic layers, first transistors provided in an array in the first and second directions, and electrically connected to the magnetoresistive elements, respectively, switching units each electrically connected to corresponding ones of the first transistors in series, and each including at least one second transistor, wherein the first magnetic layers are separated from each other in the first and second directions, and the second magnetic layers are continuously provided in the first and second directions.

公开(公告)号：US20180268887A1

公开(公告)日：2018-09-20

申请号：US15700592

申请日：2017-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Masaki ENDO ,  Tadaomi Daibou ,  Shumpei Omine ,  Junichi Ito ,  Akiyuki Murayama ,  Takeshi Iwasaki

IPC: G11C11/16 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22

CPC classification number: G11C11/161 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0061 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive element according to an embodiment includes: a first nonmagnetic layer; a first magnetic layer; a second magnetic layer disposed between the first nonmagnetic layer and the first magnetic layer; a second nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; a third nonmagnetic layer disposed between the second nonmagnetic layer and the second magnetic layer; and a third magnetic layer disposed between the second nonmagnetic layer and the third nonmagnetic layer, wherein elements constituting the second magnetic layer at least partially differ from elements constituting the third magnetic layer, a relative permittivity of the first nonmagnetic layer is at least 10, and the third nonmagnetic layer contains at least one element selected from the group consisting of Nb, Ta, Mo, W, Hf, Zr, Ti, Sc, V, Cr, Mn, Fe, Co, Ni, Mg, Al, Ru, Ir, Rh, Pd, Pt, Cu, Ag, and Au.

公开(公告)号：US10079266B2

公开(公告)日：2018-09-18

申请号：US15122129

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Christopher J. Wiegand ,  Md Tofizur Rahman ,  Oleg Golonzka ,  Anant H. Jahagirdar ,  Mengcheng Lu

IPC: H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Embodiments of the present disclosure describe techniques and configurations associated with modulation of magnetic properties through implantation. In one embodiment, a method includes providing a substrate having an integrated circuit (IC) structure disposed on the substrate, the IC structure including a magnetizable material, implanting at least a portion of the magnetizable material with a dopant and magnetizing the magnetizable material, wherein said magnetizing is inhibited in the implanted portion of the magnetizable material. Other embodiments may be described and/or claimed.

公开(公告)号：US20180261271A1

公开(公告)日：2018-09-13

申请号：US15919071

申请日：2018-03-12

Applicant: Simon Fraser University

Inventor： Zachary Raymond Nunn ,  Erol Girt

IPC: G11C11/16 ,  G11C11/15 ,  G01R33/12 ,  H01L43/08 ,  H01F1/01

CPC classification number: G11C11/1673 ,  G01R33/093 ,  G01R33/098 ,  G01R33/1284 ,  G11C11/15 ,  G11C11/161 ,  G11C11/1675 ,  H01F1/015 ,  H01F1/017 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetic device comprising having a first magnetic layer having a first magnetization direction, a second magnetic layer having a second magnetization direction, a first coupling layer interposed between the first and second magnetic layers, a third magnetic layer having a third magnetization direction, a first magnetoresistive layer interposed between the third magnetic layer and the second magnetic layer, and a circuit connected to one or more of the layers of the magnetic device by at least a pair of leads. The circuit is configured to determine a change in resistance between the pair of leads. The change in resistance is based at least in part on a change in an angular relationship between the third magnetization direction and the second magnetization direction caused by an external magnetic field or a current passing through at least a portion of the device.

公开(公告)号：US20180261269A1

公开(公告)日：2018-09-13

申请号：US14588819

申请日：2015-01-02

Applicant: Jannier Maximo Roiz Wilson

Inventor： Jannier Maximo Roiz Wilson

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

CPC classification number: G11C11/161 ,  G11C11/1659 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: The present invention sets forth a new approach to Spin Transfer Torque MRAM that relies on 3D shape anisotropy and bulk-like ferromagnetic material properties in the free-layer to lower the write current and allow high TMR to a great extent independently of cell size and for any desired thermal stability of the cell.

公开(公告)号：US20180248553A1

公开(公告)日：2018-08-30

申请号：US15959698

申请日：2018-04-23

Applicant: Georgia Tech Research Corporation

Inventor： Chenyun Pan ,  Sourav Dutta ,  Azad Naeemi

IPC: H03K19/20 ,  H01F10/32 ,  H01F10/14 ,  H01F10/16 ,  H01L43/10 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

CPC classification number: H03K19/20 ,  H01F10/14 ,  H01F10/16 ,  H01F10/3218 ,  H01L27/22 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.

公开(公告)号：US20180240964A1

公开(公告)日：2018-08-23

申请号：US15751102

申请日：2015-09-10

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Sasikanth Manipatruni ,  Anurag Chaudhry ,  Ian A. Young

IPC: H01L43/04 ,  H01L43/08 ,  H01L43/10 ,  H01L43/06 ,  H03K19/18

CPC classification number: H01L43/04 ,  H01L43/065 ,  H01L43/08 ,  H01L43/10 ,  H03K19/18

Abstract: Described is an apparatus which comprises: a first non-magnetic conductor; a first spin orbit coupling (SOC) layer coupled to the first non-magnetic conductor; a first ferromagnet (FM) coupled to the SOC layer; a second FM; and an insulating FM sandwiched between the first and second FMs.

公开(公告)号：US20180240655A1

公开(公告)日：2018-08-23

申请号：US15890694

申请日：2018-02-07

Applicant: APPLIED MATERIALS, INC.

Inventor： HANBING WU ,  ANANTHA K. SUBRAMANI ,  ASHISH GOEL ,  XIAODONG WANG ,  WEI W. WANG ,  RONGJUN WANG ,  CHI HONG CHING

IPC: H01J37/34 ,  H01L43/12

CPC classification number: H01J37/3441 ,  H01J37/3429 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Methods and apparatus for processing substrates with a multi-cathode chamber. The multi-cathode chamber includes a shield with a plurality of holes and a plurality of shunts. The shield is rotatable to orient the holes and shunts with a plurality of cathodes located above the shield. The shunts interact with magnets from the cathodes to prevent interference during processing. The shield can be raised and lowered to adjust gapping between a target of a cathode and a hole to provide a dark space during processing.