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公开(公告)号：US3623071A
公开(公告)日：1971-11-23
申请号：US3623071D
申请日：1970-08-24
申请人： US NAVY
发明人： BENTLYE JOHN M
摘要： An analog to digital converter that provides conversion in real time at high bit rates and accuracy without the use of a digital to analog converter and successive comparisons or subtractions of reference voltages.
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52.发明授权公开(公告)号：US12107596B2
公开(公告)日：2024-10-01
申请号：US17961845
申请日：2022-10-07
申请人： Ciena Corporation
摘要： A successive approximation register based time-to-digital converter circuit with a time difference amplifier (TDA). A first TDA which applies a gain value to a time difference between a first signal edge and a first delayed signal edge to generate a first amplified time difference signal, which is feedback to the first TDA, a second TDA which applies a gain value to a time difference between a second signal edge and a second delayed signal edge to generate a second amplified time difference signal, which is feedback to the second TDA, and a finite state machine which sets another gain value, for a next step in a N step conversion until N steps are completed, in the first and the second TDAs based on a bit value from a previous step, wherein the bit value indicates, for a step, whether the first or second amplified time difference signal is ahead.
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公开(公告)号：US11949427B2
公开(公告)日：2024-04-02
申请号：US17089457
申请日：2020-11-04
发明人： Gavin McVeigh
CPC分类号： H03M1/785 , G01L1/2268 , H03M1/0607 , H03M1/16 , H03M1/662 , H03M1/802 , H03F3/45 , H03M1/808
摘要： The present disclosure relates to a compensation circuit for compensating for an offset voltage that is present in an output signal output by a force sensor. The compensation circuit comprises: voltage divider circuitry, the voltage divider circuitry configured to receive a bias voltage that is also supplied to the force sensor and to output a control voltage derived from the bias voltage, wherein a component mismatch ratio of the voltage divider circuitry is adjustable to correspond to a component mismatch ratio of the force sensor; current generator circuitry configured to receive the control voltage and to generate a compensating current based on the received control voltage; and amplifier circuitry configured to receive the differential signal output by the force sensor and the compensating current and to output a compensated differential output signal in which the offset voltage is at least partially cancelled.
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公开(公告)号：US11870454B2
公开(公告)日：2024-01-09
申请号：US17792803
申请日：2020-01-15
申请人： LG ELECTRONICS INC.
发明人： Yigi Kwon , Byoung Han Min
摘要： According to one embodiment of the present invention, provided is an analog to digital converter. The analog-to-digital converter according to one embodiment of the present invention comprises an analog amplification unit and a flash conversion unit, wherein the analog amplification unit may have a structure in which in which two input terminal circuits that alternately operate share a single amplifier. Accordingly, the analog-to-digital converter according to one embodiment of the present invention can be implemented in a smaller area and operate at low power, and can have a high resolution while operating at a high speed.
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公开(公告)号：US20240007127A1
公开(公告)日：2024-01-04
申请号：US18254204
申请日：2020-12-21
申请人： Google LLC
CPC分类号： H03M3/426 , H03M3/498 , H03M1/0854 , H03M1/16
摘要： This disclosure describes apparatuses, methods, and techniques that enable a computing device to support a dynamic range of audio quality, varying bandwidths, varying sampling rates, numerous effective number of bits (ENOBs) resolutions, conserve power during an overall usage of the computing device, and enhance a user experience. To do so, the computing device utilizes a reconfigurable analog-to-digital converter (ADC). The reconfigurable ADC includes a successive-approximation-register (SAR) ADC, a noise-canceling circuit, and a noise-shaping circuit. The reconfigurable ADC can selectively operate in different modes of operation, in part, by enabling or disabling the noise-canceling circuit and the noise-shaping circuit.
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公开(公告)号：US09100043B2
公开(公告)日：2015-08-04
申请号：US14529396
申请日：2014-10-31
申请人： Mathias Krauβ
发明人： Mathias Krauβ
CPC分类号： H03M1/442 , H03M1/00 , H03M1/002 , H03M1/0624 , H03M1/069 , H03M1/12 , H03M1/16 , H03M1/56 , H03M1/804
摘要： A method for converting a capacitance of a precision capacitor for measurement into a digital signal is described. According to a clocking in charging processes an integration capacitor, discharged before the start of conversion, of an integrator circuit is charged by electric current obtained from a charging of the precision capacitor and in discharge processes by brief current surges in the opposite direction which are obtained from a charging of a reference capacitor, with the result that on average no charge builds up, and the number of discharge processes in a particular number of clock pulses is counted. The clocking is paused after a predetermined number of cycles. A residual voltage is converted into a digital value and the counted number of discharge processes and the particular number of clock pulses are combined with the digital value emitted by the analog-to-digital voltage converter to form a digital total result.
摘要翻译： 描述用于将用于测量的精密电容器的电容转换为数字信号的方法。 根据充电处理的时钟，积分电路的开始放电的积分电容器通过从精密电容器的充电获得的电流和通过相反方向上的短暂的电流浪涌而获得的电流充电 从参考电容器的充电中，结果平均不产生电荷，并计数特定数量的时钟脉冲中的放电过程的数量。 时钟在预定次数的周期后暂停。 剩余电压被转换为数字值，并且将计数的放电过程数和特定时钟脉冲数与由模数转换器发射的数字值组合以形成数字总结果。
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57.发明授权Logarithmic analog/digital conversion method for an analog input signal, and corresponding device 有权模拟输入信号的对数模拟/数字转换方法及相应的器件公开(公告)号：US08493252B2
公开(公告)日：2013-07-23
申请号：US13032115
申请日：2011-02-22
申请人： Jean Gorisse , Andreia Cathelin , Andreas Kaiser , Eric Kerherve
发明人： Jean Gorisse , Andreia Cathelin , Andreas Kaiser , Eric Kerherve
IPC分类号： H03M1/84
CPC分类号： H03M1/1235 , H03M1/16
摘要： A logarithmic analog to digital conversion method for an analog input signal includes a logarithmic amplification with progressive compression of the input signal delivering a sequence of several secondary analog signals. The trend of the values of at least some of the secondary signals is a function of the values of the analog input signal including regions corresponding to a linear trend of the secondary signals as a function of that of the input signal expressed in a logarithmic scale. The method also includes a comparison of at least some of the secondary signals of the sequence with a common reference signal whose value lies within each of regions, supplying a thermometric code information item, and a generation of a first digital word from the thermometric code information item.
摘要翻译： 用于模拟输入信号的对数模数转换方法包括对输入信号进行逐次压缩的对数放大，该输入信号提供多个次级模拟信号的序列。 至少一些次级信号的值的趋势是模拟输入信号的值的函数，该模拟输入信号包括与辅助信号的线性趋势相对应的区域作为以对数刻度表示的输入信号的函数的函数。 该方法还包括将序列中的至少一些辅助信号与其值位于每个区域内的公共参考信号进行比较，提供测温代码信息项，以及从测温代码信息生成第一数字字 项目。
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58.发明申请LOGARITHMIC ANALOG/DIGITAL CONVERSION METHOD FOR AN ANALOG INPUT SIGNAL, AND CORRESPONDING DEVICE 有权用于模拟输入信号的对数模拟/数字转换方法及相应的器件公开(公告)号：US20110205093A1
公开(公告)日：2011-08-25
申请号：US13032115
申请日：2011-02-22
申请人： Jean GORISSE , Andreia Cathelin , Andreas Kaiser , Eric Kerherve
发明人： Jean GORISSE , Andreia Cathelin , Andreas Kaiser , Eric Kerherve
CPC分类号： H03M1/1235 , H03M1/16
摘要： A logarithmic analog to digital conversion method for an analog input signal includes a logarithmic amplification with progressive compression of the input signal delivering a sequence of several secondary analog signals. The trend of the values of at least some of the secondary signals is a function of the values of the analog input signal including regions corresponding to a linear trend of the secondary signals as a function of that of the input signal expressed in a logarithmic scale. The method also includes a comparison of at least some of the secondary signals of the sequence with a common reference signal whose value lies within each of regions, supplying a thermometric code information item, and a generation of a first digital word from the thermometric code information item.
摘要翻译： 用于模拟输入信号的对数模数转换方法包括对输入信号进行逐次压缩的对数放大，该输入信号提供多个次级模拟信号的序列。 至少一些次级信号的值的趋势是模拟输入信号的值的函数，该模拟输入信号包括与辅助信号的线性趋势相对应的区域作为以对数标度表示的输入信号的函数的函数。 该方法还包括将序列中的至少一些辅助信号与其值位于每个区域内的公共参考信号进行比较，提供测温代码信息项，以及从测温代码信息生成第一数字字 项目。
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公开(公告)号：US20110084866A1
公开(公告)日：2011-04-14
申请号：US12693713
申请日：2010-01-26
申请人： Pochin HSU
发明人： Pochin HSU
IPC分类号： H03M1/12
摘要： The configuration of a successive approximation analog to digital converter (ADC) and a method thereof are provided in the present invention. The proposed configuration includes a comparator having an inverting input terminal, a non-inverting input terminal and an output terminal outputting a comparison result, a most significant bit ADC coupled to the non-inverting input terminal, and a least significant bit ADC coupled to the inverting input terminal.
摘要翻译： 在本发明中提供了逐次逼近模数转换器（ADC）的配置及其方法。 所提出的配置包括具有反相输入端子，非反相输入端子和输出比较结果的输出端子的比较器，耦合到非反相输入端子的最高有效位ADC和耦合到非反相输入端口的最低有效位ADC 反相输入端子。
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60.发明授权公开(公告)号：US06784822B1
公开(公告)日：2004-08-31
申请号：US10693215
申请日：2003-10-24
申请人： Michael A. Nix , Ahmed Younis
发明人： Michael A. Nix , Ahmed Younis
IPC分类号： H03M138
摘要： A voltage of an input analog signal (105 or 405) can be converted to a signal whose frequency is dependent upon the analog input signal (135 or 435). A frequency divider (115 or 415) can be configured to convert the frequency dependent signal to a frequency divided signal (140 or 440). A first frequency detector (420a) or time detector (120a) can be configured to determine the frequency of the frequency divided signal, thereby creating a first output signal (145a or 445a). A second frequency detector (420b) or time detector (120b) can be configured to determine the frequency of the frequency dependent or non-frequency divided signal, thereby creating a second output signal (145b or 445b). The first and second output signals can be post-processed to generate a digital output signal (130 or 430) that is representative of the input analog signal.
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