公开(公告)号：US4652463A

公开(公告)日：1987-03-24

申请号：US697682

申请日：1985-02-01

申请人： John W. Peters

发明人： John W. Peters

IPC分类号： C23C16/40 ,  B05D3/06

CPC分类号： C23C16/407 ,  Y10S438/953

摘要： The specification discloses a low-temperature process for depositing a layer of a conductive oxide of a chosen metal, such as tin oxide, on the surface of a substrate while simultaneously avoiding damage to the substrate. The process comprises exposing the substrate to a selected vapor phase reactant containing the chosen metal, such as tetramethyl tin, in the presence of neutral, charge-free oxygen atoms formed in a manner which avoids the generation of charged particles and high energy radiation that would damage the substrate. The oxygen atoms react with the vapor phase reactant to form the conductive oxide, which deposits as a layer on the surface of the substrate. In a preferred process embodiment, the neutral oxygen atoms are photochemically generated. This process is especially useful for depositing a layer of a transparent conductive oxide on the surface of a radiation-hardened device while maintaining the radiation-hardness of the device.

摘要翻译： 该说明书公开了一种低温工艺，用于在衬底的表面上沉积所选金属如氧化锡的导电氧化物层，同时避免对衬底的损坏。 该方法包括将基底暴露于所选择的含有所选择的金属的气相反应物，例如四甲基锡，在中性无电荷的氧原子的存在下，以避免产生带电粒子和高能量辐射的方式形成， 损坏基板。 氧原子与气相反应物反应形成导电氧化物，其在衬底的表面上沉积成一层。 在优选的方法实施方案中，光氧化生成中性氧原子。 该方法对于在辐射硬化装置的表面上沉积透明导电氧化物层同时保持装置的辐射硬度是特别有用的。

公开(公告)号：US4608452A

公开(公告)日：1986-08-26

申请号：US669140

申请日：1984-11-07

申请人： Irving Weinberg ,  Henry W. Brandhorst, Jr.

发明人： Irving Weinberg ,  Henry W. Brandhorst, Jr.

IPC分类号： H01L31/0288 ,  H01L31/068 ,  H01L31/18 ,  H01L31/06

CPC分类号： H01L31/1804 ,  H01L31/0288 ,  H01L31/068 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S438/919 ,  Y10S438/953

摘要： The resistance to radiation damage of an n.sup.+ p boron doped silicon solar cell is improved by lithium counterdoping. Even though lithium is an n-dopant in silicon, the lithium is introduced in small enough quantities so that the cell base remains p-type.The lithium is introduced into the solar cell wafer 10 by implantation of lithium ions whose energy is about 50 keV. After this lithium implantation, the wafer is annealed in a nitrogen atmosphere at 375.degree. C. for two hours.

摘要翻译： 通过锂反掺杂改善了n + p硼掺杂硅太阳能电池的耐辐射损伤。 尽管锂是硅中的n-掺杂剂，但是以足够少的量引入锂，使得电池基底保持p型。 通过注入能量约为50keV的锂离子将锂引入到太阳能电池晶片10中。 在该锂注入之后，将晶片在氮气气氛中在375℃下退火2小时。

公开(公告)号：US4468411A

公开(公告)日：1984-08-28

申请号：US365724

申请日：1982-04-05

申请人： James W. Sloan ,  Truoc T. Tran ,  Frank T. Jones, III

发明人： James W. Sloan ,  Truoc T. Tran ,  Frank T. Jones, III

IPC分类号： H01L21/312 ,  H01L23/556 ,  H01L23/00

CPC分类号： H01L23/556 ,  H01L21/312 ,  H01L2224/49171 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  Y10S438/953

摘要： A controlled quantity of a liquid polyimide precursor compound is deposited on the active surface of an integrated circuit die which has been prepared for packaging, and thereafter cured using a two step curing process to develop a polyimide coating of sufficient thickness to provide alpha particle protection for the die once packaged.

摘要翻译： 将控制量的液体聚酰亚胺前体化合物沉积在已经制备用于包装的集成电路管芯的有效表面上，然后使用两步固化方法固化，以开发足够厚度的聚酰亚胺涂层，以提供α粒子保护 一次封装包装。

公开(公告)号：US4423548A

公开(公告)日：1984-01-03

申请号：US280190

申请日：1981-07-06

申请人： Terry S. Hulseweh

发明人： Terry S. Hulseweh

IPC分类号： G11C5/00 ,  H01L21/56

CPC分类号： G11C5/005 ,  Y10S438/953

摘要： A structure is provided which affords radiation protection to semiconductor devices and which specifically prevents soft failures in semiconductor memories caused by alpha particle radiation. The protection is provided by a metallic radiation shield formed on but insulated from the semiconductor memory array. The radiation shield is formed on the semiconductor devices while they are still in wafer form but after the normal device fabrication has been completed.

摘要翻译： 提供了提供对半导体器件的辐射保护并且具体地防止由α粒子辐射引起的半导体存储器中的软故障的结构。 保护由在半导体存储器阵列上形成绝缘的金属辐射屏蔽提供。 在半导体器件仍然是晶片形式但是在正常的器件制造完成之后，形成辐射屏蔽。

公开(公告)号：US4328610A

公开(公告)日：1982-05-11

申请号：US143867

申请日：1980-04-25

申请人： Charles E. Thompson ,  Roger G. Newell

发明人： Charles E. Thompson ,  Roger G. Newell

IPC分类号： H01L21/263 ,  H01L23/556 ,  H01L27/108 ,  H01L7/54

CPC分类号： H01L27/10805 ,  H01L21/263 ,  H01L23/556 ,  H01L2924/0002 ,  Y10S438/953 ,  Y10S438/98

摘要： Alpha-particle induced errors in integrated circuits, especially those used for memory storage, are reduced by subjecting the partially completed, or fully completed, integrated circuits to neutron irradiation. This irradiation creates "traps" in the single crystalline semiconductor substrates of the integrated circuits for any unwanted charged particles that are produced by alpha particle radiation. Consequently, such unwanted charged particles do not disrupt the integrity of any data stored in the circuit. In one embodiment, the neutron irradiation is applied during wafer fabrication and, in a second embodiment, the irradiation is applied after wafer fabrication but before packaging of the circuit, and in the third embodiment the irradiation is applied after a completion of the packaging step of the integrated circuits.

摘要翻译： 通过对部分完成或完全完成的集成电路进行中子照射，集成电路中特别是用于存储器存储的α粒子感应误差减小。 这种照射在由α粒子辐射产生的任何不需要的带电粒子的集成电路的单晶半导体衬底中产生“陷阱”。 因此，这种不需要的带电粒子不会破坏存储在电路中的任何数据的完整性。 在一个实施例中，在晶片制造期间施加中子辐射，并且在第二实施例中，在晶片制造之后但在电路封装之前施加照射，并且在第三实施例中，在完成包装步骤之后施加照射 集成电路。

公开(公告)号：US4323405A

公开(公告)日：1982-04-06

申请号：US105196

申请日：1979-12-19

申请人： Koichi Uno ,  Shinichi Murakami

发明人： Koichi Uno ,  Shinichi Murakami

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L23/02 ,  H01L23/057 ,  H01L23/556 ,  H01L27/06 ,  H01L23/06

CPC分类号： H01L23/057 ,  H01L23/556 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16152 ,  H01L2924/1617 ,  Y10S438/953

摘要： A hermetic cap member of a casing for a semiconductor memory element is provided with a protection layer on a recessed surface facing the memory element. The protection layer is of at least one material which does not emit alpha particles and has a thickness sufficient to prevent alpha particles from being emitted from the cap member onto the memory element. Specifically, the protection layer may be a plate of a pertinent one of the following silicon of high purity, 42 alloy, or Kovar and is attached to the cap member by the use of an adhesive of glass frit. Alternatively, the protection layer may be made from a metallic paste of silver, silver-palladium, or gold-palladium by firing the same onto the cap member. The protection layer may also be magnesium oxide formed by the use of a plasma spray process. As a further alternative, the protection layer may consist of a plurality of materials.

摘要翻译： 用于半导体存储元件的壳体的密封盖构件在面向存储元件的凹入表面上设置有保护层。 保护层是至少一种不发射α粒子并且具有足以防止α粒子从盖构件发射到存储元件上的厚度的材料。 具体地，保护层可以是以下相关的高纯度硅，42合金或科瓦尔之一的板，并且通过使用玻璃料的粘合剂附接到盖构件。 或者，保护层可以由银，银 - 钯或金 - 钯的金属膏制成，通过将其烧制到盖构件上。 保护层也可以是通过使用等离子体喷涂工艺形成的氧化镁。 作为另一替代方案，保护层可以由多种材料组成。

公开(公告)号：US4288911A

公开(公告)日：1981-09-15

申请号：US106127

申请日：1979-12-21

申请人： Kenneth A. Ports

发明人： Kenneth A. Ports

IPC分类号： G01R31/28 ,  H01L21/26 ,  H01L21/66 ,  H01L21/423

CPC分类号： G01R31/2881 ,  G01R31/2856 ,  H01L21/26 ,  G01R31/2831 ,  Y10S148/162 ,  Y10S438/953

摘要： Integrated circuits in dice on a wafer are qualified by providing two sets of conductors connected to each die by fusible elements, biasing the dice using said conductors during exposure to a qualifying environment, testing the fusible elements, removing the conductors and testing the circuits. Where the environment is gamma radiation, the fusible elements are tested before annealing of radiation damage and the circuits are tested before and after annealing.

摘要翻译： 通过提供通过可熔元件连接到每个管芯的两组导体来限定晶片上的晶片中的集成电路，在暴露于限定环境期间使用所述导体偏置裸片，测试可熔元件，去除导体和测试电路。 在环境为伽马辐射的地方，在辐射损伤退火之前测试易熔元件，并在退火前后测试电路。

公开(公告)号：US4247862A

公开(公告)日：1981-01-27

申请号：US922225

申请日：1978-07-05

申请人： Raphael Klein

发明人： Raphael Klein

IPC分类号： H01L21/265 ,  H01L23/556 ,  H01L27/108 ,  H01L27/04

CPC分类号： H01L21/26513 ,  H01L23/556 ,  H01L27/108 ,  H01L2924/0002 ,  Y10S257/921 ,  Y10S438/953

摘要： A structure and method for preventing minority carriers caused by an alpha particle, or the like, from drifting into storage regions and causing a false data bit. In a high density MOS circuit, a single alpha particle including one originating within the substrate or circuit package can generate enough carriers to give a false data bit. A minority carrier reflective barrier is employed to prevent substantial numbers of minority carriers from drifting into the active layer. In the presently preferred embodiment, this barrier is formed by ion implanting the upper surface of the substrate.

摘要翻译： 用于防止由α粒子等引起的少数载体的结构和方法漂移到存储区域并导致伪数据位。 在高密度MOS电路中，包括源于衬底或电路封装的单个α粒子可以产生足够的载流子以给出假数据位。 采用少数载流子反射屏障来防止大量少数载流子漂移到活性层中。 在目前优选的实施例中，通过离子注入衬底的上表面形成该阻挡层。

公开(公告)号：US3933530A

公开(公告)日：1976-01-20

申请号：US544702

申请日：1975-01-28

申请人： Charles William Mueller ,  Edward Curtis Douglas ,  Chung Pao Wu

发明人： Charles William Mueller ,  Edward Curtis Douglas ,  Chung Pao Wu

IPC分类号： H01L21/3115 ,  H01L29/00 ,  H01L21/265

CPC分类号： H01L21/31155 ,  H01L29/00 ,  Y10S257/906 ,  Y10S438/953

摘要： In one embodiment, a semiconductor device, such as an insulated-gate-field-effect-transistor (IGFET), is simultaneously radiation hardened with Al ions and its threshold voltage stabilized with halide ions, such as Cl ions, by bombarding a silicon dioxide gate insulator of the device with molecular ions of an aluminum halide, such as AlCl.sub.2 .sup.+ ions. In another embodiment, a surface (target) of silicon is bombarded with molecular AlCl.sub.2 .sup.+ ions to ion implant separate Al ions and Cl ions. There, an oxide layer subsequently thermally grown on the bombarded surface includes the Al ions and the Cl ions, and the oxide layer is radiation hardened and gettered.

摘要翻译： 在一个实施例中，诸如绝缘栅场效应晶体管（IGFET）的半导体器件同时被Al离子放射硬化，并且其阈值电压通过用二氧化硅轰击而被诸如Cl离子的卤素离子稳定 具有铝卤化物的分子离子的器件的栅极绝缘体，例如AlCl 2 +离子。 在另一个实施方案中，硅的表面（靶）用分子AlCl 2+轰击离子注入分离的Al离子和Cl离子。 在那里，随后在轰击表面上热生长的氧化物层包括Al离子和Cl离子，并且氧化物层被辐射硬化和吸收。

公开(公告)号：US07518218B2

公开(公告)日：2009-04-14

申请号：US11071730

申请日：2005-03-03

申请人： Harry N. Gardner

发明人： Harry N. Gardner

IPC分类号： H01L23/552

CPC分类号： H01L27/092 ,  H01L29/402 ,  Y10S257/921 ,  Y10S438/953

摘要： A total ionizing dose suppression architecture for a transistor and a transistor circuit uses an “end cap” metal structure that is connected to the lowest potential voltage to overcome the tendency of negative charge buildup during exposure to ionizing radiation. The suppression architecture uses the field established by coupling the metal structure to the lowest potential voltage to steer the charge away from the critical field (inter-device) and keeps non-local charge from migrating to the “birds-beak” region of the transistor, preventing further charge buildup. The “end cap” structure seals off the “birds-beak” region and isolates the critical area. The critical area charge is source starved of an outside charge. Outside charge migrating close to the induced field is repelled away from the critical region. The architecture is further extended to suppress leakage current between adjacent wells biased to differential potentials.

摘要翻译： 用于晶体管和晶体管电路的总电离剂量抑制架构使用连接到最低电位电压的“端帽”金属结构，以克服暴露于电离辐射期间负电荷积聚的趋势。 抑制架构使用通过将金属结构耦合到最低电位电压而建立的电场，以将电荷转移到临界场（器件间），并使非局部电荷迁移到晶体管的“鸟嘴”区域 ，防止进一步的电荷积聚。 “端帽”结构封闭了“鸟嘴”地区，隔离了关键区域。 关键区域电荷是源于缺乏外部电荷。 接近感应场迁移的外部电荷被排除在关键区域之外。 该结构被进一步扩展以抑制偏向差分电位的相邻阱之间的泄漏电流。