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    TEXTURE PROCESSOR BASED RAY TRACING ACCELERATION METHOD AND SYSTEM
    622.
    发明申请
    TEXTURE PROCESSOR BASED RAY TRACING ACCELERATION METHOD AND SYSTEM 审中-公开

    公开(公告)号：US20190197761A1

    公开(公告)日：2019-06-27

    申请号：US15853207

    申请日：2017-12-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Skyler Jonathon Saleh ,  Maxim V. Kazakov ,  Vineet Goel

    IPC: G06T15/06 ,  G06T15/04

    CPC classification number: G06T15/06 ,  G06T15/04

    Abstract: A texture processor based ray tracing accelerator method and system are described. The system includes a shader, texture processor (TP) and cache, which are interconnected. The TP includes a texture address unit (TA), a texture cache processor (TCP), a filter pipeline unit and a ray intersection engine. The shader sends a texture instruction which contains ray data and a pointer to a bounded volume hierarchy (BVH) node to the TA. The TCP uses an address provided by the TA to fetch BVH node data from the cache. The ray intersection engine performs ray-BVH node type intersection testing using the ray data and the BVH node data. The intersection testing results and indications for BVH traversal are returned to the shader via a texture data return path. The shader reviews the intersection results and the indications to decide how to traverse to the next BVH node.

    Reduced setup time clock gating circuit
    624.
    发明授权
    Reduced setup time clock gating circuit 有权

    公开(公告)号：US10331196B2

    公开(公告)日：2019-06-25

    申请号：US15626847

    申请日：2017-06-19

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Russell Schreiber

    IPC: G06F1/324 ,  H03K5/159 ,  G06F1/3296 ,  G06F1/3287

    Abstract: A system and method for providing efficient clock gating capability for functional units are described. A functional unit uses a clock gating circuit for power management. A setup time of a single device propagation delay is provided for a received enable signal. When each of a clock signal, the enable signal and a delayed clock signal is asserted, an evaluate node of the clock gating circuit is discharged. When each of the clock signal and a second clock signal is asserted and the enable signal is negated, the evaluate node is left floating for a duration equal to the hold time. Afterward, the devices in a delayed onset keeper are turned on and the evaluate node has a path to the power supply. When the clock signal is negated, the evaluate node is precharged.

    ADAPTIVE QUANTIZATION FOR NEURAL NETWORKS
    625.
    发明申请
    ADAPTIVE QUANTIZATION FOR NEURAL NETWORKS 审中-公开

    公开(公告)号：US20190188557A1

    公开(公告)日：2019-06-20

    申请号：US15849617

    申请日：2017-12-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Daniel I. Lowell ,  Sergey Voronov ,  Mayank Daga

    IPC: G06N3/063 ,  G06N3/08

    CPC classification number: G06N3/063 ,  G06N3/08

    Abstract: Methods, devices, systems, and instructions for adaptive quantization in an artificial neural network (ANN) calculate a distribution of ANN information; select a quantization function from a set of quantization functions based on the distribution; apply the quantization function to the ANN information to generate quantized ANN information; load the quantized ANN information into the ANN; and generate an output based on the quantized ANN information. Some examples recalculate the distribution of ANN information and reselect the quantization function from the set of quantization functions based on the resampled distribution if the output does not sufficiently correlate with a known correct output. In some examples, the ANN information includes a set of training data. In some examples, the ANN information includes a plurality of link weights.

    System and method for energy reduction based on history of reliability of a system
    627.
    发明授权
    System and method for energy reduction based on history of reliability of a system 有权

    公开(公告)号：US10318363B2

    公开(公告)日：2019-06-11

    申请号：US15338172

    申请日：2016-10-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Greg Sadowski ,  Steven E. Raasch ,  Shomit N. Das ,  Wayne Burleson

    IPC: G06F11/00 ,  G06F11/30 ,  G06F11/34

    Abstract: A system and method for managing operating parameters within a system for optimal power and reliability are described. A device includes a functional unit and a corresponding reliability evaluator. The functional unit provides reliability information to one or more reliability monitors, which translate the information to reliability values. The reliability evaluator determines an overall reliability level for the system based on the reliability values. The reliability monitor compares the actual usage values and the expected usage values. When system has maintained a relatively high level of reliability for a given time interval, the reliability evaluator sends an indication to update operating parameters to reduce reliability of the system, which also reduces power consumption for the system.

    Secure system memory training
    629.
    发明授权
    Secure system memory training 有权

    公开(公告)号：US10311236B2

    公开(公告)日：2019-06-04

    申请号：US15358640

    申请日：2016-11-22

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Kathirkamanathan Nadarajah ,  Oswin Housty ,  Sergey Blotsky ,  Tan Peng ,  Hary Devapriyan Mahesan

    IPC: G06F9/00 ,  G06F15/177 ,  G06F21/57 ,  G06F9/4401

    Abstract: Systems, apparatuses, and methods for performing secure system memory training are disclosed. In one embodiment, a system includes a boot media, a security processor with a first memory, a system memory, and one or more main processors coupled to the system memory. The security processor is configured to retrieve first data from the boot media and store and authenticate the first data in the first memory. The first data includes a first set of instructions which are executable to retrieve, from the boot media, a configuration block with system memory training parameters. The security processor also executes a second set of instructions to initialize and train the system memory using the training parameters. After training the system memory, the security processor retrieves, authenticates, and stores boot code in the system memory and releases the one or more main processors from reset to execute the boot code.

    Memory including side-car arrays with irregular sized entries
    630.
    发明授权
    Memory including side-car arrays with irregular sized entries 有权

    公开(公告)号：US10311191B2

    公开(公告)日：2019-06-04

    申请号：US15416731

    申请日：2017-01-26

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John J. Wuu ,  Patrick J. Shyvers ,  Ryan Alan Selby

    IPC: G06F17/50 ,  G11C7/06 ,  G11C7/20 ,  G11C5/02

    Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. A memory macro block includes at least a primary array and a sidecar array. The primary array stores a first portion of a memory line and the sidecar array stores a second smaller portion of the memory line being accessed. The primary array and the sidecar array have different heights. The height of the sidecar array is based on a notch height in at least one corner of the memory macro block. The notch creates on-die space for s reserved area on the die. The notches result in cross-shaped, T-shaped, and/or L-shaped memory macro blocks.

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