公开(公告)号：US08933737B1

公开(公告)日：2015-01-13

申请号：US14046041

申请日：2013-10-04

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V.

Inventor： Kallol Chatterjee ,  Nitin Agarwal ,  Junaid Yousuf ,  Nitin Gupta ,  Pierre Dautriche

IPC: H03L7/06 ,  H03L7/095

CPC classification number: H03L7/095

Abstract: A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.

Abstract translation: 变频时钟发生器。 在方面中，时钟发生器包括下垂检测器电路，其被配置为监视对集成电路的电压供应。 如果电源电压低于特定阈值，则可以设置下降电压标志，使得频率锁定环路被触发到用于处理电源电压的电压下降的下降电压模式。 作为响应，通过将电流从电流控制信号吸收到振荡器来减小输入到产生系统时钟信号的振荡器的电流控制信号。 这将立即降低系统时钟频率。 当去除电流路径以吸收一些电流时，这种状态保持直到电压下降消散。

公开(公告)号：US20140370668A1

公开(公告)日：2014-12-18

申请号：US14177592

申请日：2014-02-11

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： Heimanu NIEBOJEWSKI ,  Yves MORAND ,  Maud VINET

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L21/28123 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/76205 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603

Abstract: The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack.

Abstract translation: 本发明涉及一种晶体管的制造方法，其包括制备绝缘体上半导体层的一叠叠层，其中至少一个衬底上依次配置绝缘层和初始半导体层。 该方法包括形成从绝缘层的顶面延伸的至少一个氧化物焊盘，形成由半导体材料制成的附加层，该半导体材料覆盖氧化物焊盘并且旨在形成用于晶体管的沟道，形成栅极 堆叠在氧化物垫的上方，并且在栅极堆叠的任一侧上形成源极和漏极。

公开(公告)号：US20140367828A1

公开(公告)日：2014-12-18

申请号：US14306934

申请日：2014-06-17

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat a L'Energie Atomique et aux Energies Alternatives

Inventor： Jean-Philippe Colonna ,  Sylvain Joblot ,  Thierry Mourier ,  Olivier Guiller

IPC: H01L49/02 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L28/40 ,  H01G2/103 ,  H01G4/236 ,  H01G4/35 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/642 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a substrate and an integrated-circuit interconnect on a first side. A capacitor passes through the substrate possessing a first electrode having a first contact face electrically coupled to a first electrically conductive zone placed on a second side of the substrate and a second electrode electrically coupled to the interconnect. A through-silicon via passes through the substrate having at one end a first contact face electrically coupled to a second electrically conductive zone placed on said second side of the substrate and at the other end a part electrically coupled to the interconnect part. The two first contact faces are located in the same plane.

Abstract translation: 一种器件包括在第一侧上的衬底和集成电路互连。 电容器通过具有第一电极的基板，该第一电极具有电耦合到放置在基板的第二侧上的第一导电区域的第一接触面和与该互连件电耦合的第二电极。 透硅通孔穿过基板，其一端具有电耦合到位于基板的所述第二侧上的第二导电区的第一接触面，另一端电耦合到互连部分。 两个第一接触面位于同一平面内。

公开(公告)号：US20140342524A1

公开(公告)日：2014-11-20

申请号：US14447699

申请日：2014-07-31

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Grégory Bidal ,  Laurent Favennec ,  Raul Andres Bianchi

IPC: H01L21/762 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/76232 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.

Abstract translation: 一种集成电路，其包括限定由单晶半导体材料制成的有源区域的至少一个隔离沟槽，所述或每个沟槽包括上部，该上部包括封装沟槽的下部的绝缘层，所述下部至少部分地被埋置 在活性区域和包含氮或碳的包封层。

公开(公告)号：US20140291778A1

公开(公告)日：2014-10-02

申请号：US14226554

申请日：2014-03-26

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Michele Vaiana ,  Daniele Casella ,  Giuseppe Bruno ,  Rosario Cariola ,  Benoit Gautheron

IPC: G01N27/22 ,  H01L49/02

CPC classification number: G01N27/225 ,  H01L28/40

Abstract: An integrated capacitive-type humidity sensor formed in a semiconductor chip integrating a sensing capacitor and a reference capacitor. Each of the sensing and reference capacitors have at least a first electrode and at least a second electrode, the first and second electrodes of each of the sensing and reference capacitors being arranged at distance and mutually insulated. A hygroscopic layer extends on the sensing and reference capacitors and a conductive shielding region extends on the reference capacitor but not on the sensing capacitor.

Abstract translation: 集成电容型湿度传感器，形成在集成感测电容器和参考电容器的半导体芯片中。 感测和参考电容器中的每一个具有至少第一电极和至少第二电极，每个感测和参考电容器的第一和第二电极被布置成距离并相互绝缘。 吸湿层在感测和参考电容器上延伸，导电屏蔽区域在参考电容器上延伸，但不在感测电容器上。

公开(公告)号：US20140217541A1

公开(公告)日：2014-08-07

申请号：US14247084

申请日：2014-04-07

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Michel Marty ,  François Roy ,  Jens Prima

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/1463 ,  H01L27/14683 ,  H01L27/14687 ,  H01L27/14689

Abstract: A method for forming a back-side illuminated image sensor, including the steps of: a) forming, from the front surface, doped polysilicon regions, of a conductivity type opposite to that of the substrate, extending in depth orthogonally to the front surface and emerging into the first layer; b) thinning the substrate from its rear surface to reach the polysilicon regions, while keeping a strip of the first layer; c) depositing, on the rear surface of the thinned substrate, a doped amorphous silicon layer, of a conductivity type opposite to that of the substrate; and d) annealing at a temperature capable of transforming the amorphous silicon layer into a crystallized layer.

Abstract translation: 一种用于形成背面照明图像传感器的方法，包括以下步骤：a）从前表面形成与衬底相反的导电类型的掺杂多晶硅区域，其垂直于正面延伸， 进入第一层; b）使衬底从其后表面变薄到达多晶硅区域，同时保持第一层的条带; c）在所述薄化衬底的后表面上沉积与所述衬底相反的导电类型的掺杂非晶硅层; 和d）在能够将非晶硅层转变成结晶层的温度下退火。

公开(公告)号：US20140210105A1

公开(公告)日：2014-07-31

申请号：US14167065

申请日：2014-01-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Vincent FARYS

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76895 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention concerns a method comprising: forming a plurality of parallel lines (502, 504, 506) of a sacrificial material over a layer of conductive material (510) of an integrated circuit, said parallel lines being separated by trenches, at least one of said lines being interrupted along its length by an opening (516) dividing it into first and second line portions (504A, 504B) separated by a space (S); forming spacers (522, 524, 526, 528, 530) in said trenches on lateral sides of said line portions and filling at least a bottom part of said opening between the line portions; removing the sacrificial material by etching; and forming interconnection lines (302, 304A, 304B, 306A, 306B, 308, 310) of said conductive material based on a pattern defined by said spacers.

Abstract translation: 本发明涉及一种方法，包括：在集成电路的导电材料层（510）上形成牺牲材料的多条平行线（502,504,506），所述平行线由沟槽分开，至少一个 所述线通过将其分割成由空间（S）分开的第一和第二线路部分（504A，504B）的开口（516）沿着其长度被中断; 在所述线路部分的侧面上的所述沟槽中形成间隔物（522,524,526,528,530），并且在所述线路部分之间填充所述开口的至少一部分底部; 通过蚀刻去除牺牲材料; 以及基于由所述间隔件限定的图案形成所述导电材料的互连线（302,304A，304B，306A，306B，308,310）。

公开(公告)号：US20140021586A1

公开(公告)日：2014-01-23

申请号：US14036519

申请日：2013-09-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mickael Gros-Jean

IPC: H01L49/02

CPC classification number: H01L28/40 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45542 ,  H01G4/085 ,  H01G4/1209 ,  H01G4/33 ,  H01L21/02189 ,  H01L21/02274 ,  H01L21/0228 ,  Y10T29/42 ,  Y10T29/43 ,  Y10T29/435

Abstract: A method manufactures a capacitor having polycrystalline dielectric layer between two metallic electrodes. The dielectric layer is formed by a polycrystalline growth of a dielectric metallic oxide on one of the metallic electrodes. At least one polycrystalline growth condition of the dielectric oxide is modified during the formation of the polycrystalline dielectric layer, which results in a variation of the polycrystalline properties of the dielectric oxide within the thickness of said layer.

Abstract translation: 一种制造在两个金属电极之间具有多晶介质层的电容器。 电介质层由金属电极之一上的介电金属氧化物的多晶生长形成。 在形成多晶电介质层期间，电介质氧化物的至少一个多晶生长条件被改变，这导致电介质氧化物在所述层的厚度内的多晶性质的变化。

公开(公告)号：US20140015088A1

公开(公告)日：2014-01-16

申请号：US13934683

申请日：2013-07-03

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon

IPC: H01L27/04

CPC classification number: H01L27/04 ,  G01K5/56 ,  H01L22/34 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/08057 ,  H01L2224/08111 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80012 ,  H01L2224/80097 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: A three-dimensional integrated structure is formed from a first integrated circuit with a first cavity filled with a first conductive material and a second integrated circuit with a second cavity filled with a second conductive material, the second cavity facing the first cavity. The filled first cavity forms a first element and the filled second cavity forms a second element, the first and second elements separated from each other by a cavity. The first and second conductive materials have different thermal expansion coefficients. A contact detection circuit is electrically connected to the filled first and second cavities, and is operable to sense electrical contact between the first and second conductive materials in response to a change in temperature.

Abstract translation: 三维集成结构由具有填充有第一导电材料的第一空腔的第一集成电路和具有填充有第二导电材料的第二空腔的第二集成电路形成，第二空腔面对第一空腔。 填充的第一空腔形成第一元件，并且填充的第二空腔形成第二元件，第一元件和第二元件通过空腔彼此分离。 第一和第二导电材料具有不同的热膨胀系数。 接触检测电路电连接到填充的第一和第二空腔，并且可操作以响应于温度变化来感测第一和第二导电材料之间的电接触。

公开(公告)号：US20130292952A1

公开(公告)日：2013-11-07

申请号：US13874163

申请日：2013-04-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Thomas Skotnicki ,  Onoriu Puscasu ,  Stéphan Monfray

IPC: F03G7/06

CPC classification number: F03G7/06 ,  H02N1/08

Abstract: A device for converting thermal energy into electric energy intended to be used in combination with a hot source including: a capacitor of variable capacitance, including two electrodes separated by an electrically-insulating material, one of these electrodes being deformable and being associated with an element forming a bimetallic strip, said bimetallic strip including at least two layers of materials having different thermal expansion coefficients, said bimetallic strip being free to deform when it is submitted to the heat of said hot source; a second capacitor having a first electrode connected to a first electrode of said capacitor of variable capacitance; a harvesting circuit electrically connected between the second electrode of the capacitor of variable capacitance and the second electrode of the second capacitor, said harvesting circuit being capable of conducting the current flowing between said second electrodes.

Abstract translation: 一种用于将热能转换成与热源组合使用的电能的装置，包括：可变电容的电容器，包括由电绝缘材料隔开的两个电极，这些电极中的一个可变形并与元件相关联 形成双金属条，所述双金属条包括具有不同热膨胀系数的至少两层材料，当所述双金属条被送到所述热源的热时，所述双金属条可自由变形; 第二电容器，其具有连接到所述可变电容器的电容器的第一电极的第一电极; 电连接在可变电容器的电容器的第二电极和第二电容器的第二电极之间的收集电路，所述收获电路能够传导在所述第二电极之间流动的电流。