公开(公告)号：US09337959B2

公开(公告)日：2016-05-10

申请号：US14053032

申请日：2013-10-14

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Francesco Caggioni ,  Dimitrios Giannakopoulos

IPC: H04L1/00 ,  H04J3/16 ,  H04J14/02 ,  H04J3/08 ,  H04L12/24 ,  H04J3/14 ,  H04B10/032 ,  H04B10/07

CPC classification number: H04L1/0076 ,  H04B10/032 ,  H04B10/07 ,  H04J3/085 ,  H04J3/14 ,  H04J3/1611 ,  H04J3/1652 ,  H04J14/0227 ,  H04J14/0279 ,  H04J14/0294 ,  H04J14/0297 ,  H04L1/0045 ,  H04L1/0082 ,  H04L1/0091 ,  H04L1/201 ,  H04L41/06 ,  H04L41/0677 ,  H04L2001/0097

Abstract: Systems and methods for detecting defect propagation in a networked environment comprising a defect detection component to detect defects in an aggregate signal and/or in individual signals; and a replacement signal component to generate a maintenance signal to replace defective signals detected by the defect detection component. The maintenance signal can be a uniform signal type regardless of a type associated with a defective signal. The maintenance signal can replace a defective signal during aggregation, by an aggregation component. In another aspect, the maintenance signal can replace the defective signal during de-aggregation

Abstract translation: 用于检测网络环境中的缺陷传播的系统和方法，包括用于检测聚合信号和/或各个信号中的缺陷的缺陷检测组件; 以及替换信号分量，以产生用于替换由缺陷检测部件检测到的缺陷信号的维护信号。 维护信号可以是均匀的信号类型，而不管与有缺陷的信号相关的类型。 维护信号可以通过聚合组件来代替聚合期间的有缺陷的信号。 在另一方面，维护信号可以在去聚合期间代替有缺陷的信号

公开(公告)号：US09336164B2

公开(公告)日：2016-05-10

申请号：US13644935

申请日：2012-10-04

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Kjeld Svendsen

IPC: G06F12/02 ,  G06F13/16 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F13/1642 ,  G06F11/3037 ,  G06F11/3062 ,  G06F11/3409 ,  G06F12/0215 ,  Y02D10/14 ,  Y02D10/34

Abstract: Systems and methods are provided that facilitate memory storage in a multi-bank memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends commands to the memory array and the memory array updates or retrieves data contained therein based upon the command. If the memory controller detects a pattern of memory requests, the memory controller can issue a preemptive activation request to the memory array. Accordingly, memory access overhead is reduced.

Abstract translation: 提供了便于多存储存储器件中的存储器存储的系统和方法。 该系统包含存储器控制器和通信地耦合到存储器控制器的存储器阵列。 存储器控制器将命令发送到存储器阵列，并且存储器阵列基于该命令更新或检索其中包含的数据。 如果存储器控制器检测到存储器请求的模式，则存储器控制器可以向存储器阵列发出先占激活请求。 因此，存储器访问开销降低。

公开(公告)号：US09281825B2

公开(公告)日：2016-03-08

申请号：US14469456

申请日：2014-08-26

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda Azenkot ,  Michael Grosner ,  Timothy P. Walker

IPC: H03L7/06

CPC classification number: H03L7/06

Abstract: Systems and methods for frequency synthesis using a gapper and a multi-modulus divider. A frequency synthesizer may comprise a gapper, a multi-modulus divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

Abstract translation: 使用间隙和多模式分频器进行频率合成的系统和方法。 频率合成器可以包括间隔器，多模式分频器和锁相环（PLL）。 当输出信号的频率意图大于相应的输入信号时，可以由分频器借由分频器的因子，以产生大于1的有理分频比G，以使分频器能够执行 由G.的分频。PLL能够乘以来自第一整数分频器的有间隙信号输出，并从有间隙信号衰减抖动。

公开(公告)号：US20150323956A1

公开(公告)日：2015-11-12

申请号：US14191923

申请日：2014-02-27

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Ayush Goyal ,  Phil Mitchell

IPC: G06F1/04

CPC classification number: G06F1/04 ,  G06F11/0745 ,  G06F11/0757 ,  G06F13/4027

Abstract: Various aspects provide for generating a timeout signal based on a clock counter associated with a data request. An interface component is configured for receiving a data request from a master device and forwarding the data request to a slave device. A timeout component is configured for maintaining a clock counter associated with the data request and generating a timeout signal in response to a determination that a threshold level associated with the clock counter is reached before receiving a data response associated with the data request from the slave device.

Abstract translation: 各种方面提供了基于与数据请求相关联的时钟计数器生成超时信号。 接口组件被配置为从主设备接收数据请求并将数据请求转发到从设备。 超时组件被配置用于在接收到与来自从设备的数据请求相关联的数据响应之前响应于确定与时钟计数器相关联的阈值电平来保持与数据请求相关联的时钟计数器并产生超时信号 。

公开(公告)号：US09146677B2

公开(公告)日：2015-09-29

申请号：US13752161

申请日：2013-01-28

Applicant: Applied Micro Circuits Corporation

Inventor： Kjeld Svendsen

IPC: G06F12/10 ,  G06F3/06

CPC classification number: G06F3/06 ,  G06F12/1018 ,  G06F13/1642

Abstract: The described systems and methods can facilitate efficient and effective information storage. In one embodiment a system includes a hash component, a queue request order component and a request queue component. The hash component is operable to hash a request indication. The queue request order component is operable to track a queue request order. The request queue component is operable to queue and forward requests in accordance with direction from the queue request order component. In one embodiment, the storage component maintains a request without stalling a request in an aliasing condition.

Abstract translation: 所描述的系统和方法可以促进有效和有效的信息存储。 在一个实施例中，系统包括散列组件，队列请求顺序组件和请求队列组件。 散列组件可操作以对请求指示进行散列。 队列请求命令组件可操作以跟踪队列请求顺序。 请求队列组件可用于根据队列请求命令组件的方向对请求进行排队和转发。 在一个实施例中，存储组件维持请求，而不会以混叠状态停止请求。

公开(公告)号：US09071262B1

公开(公告)日：2015-06-30

申请号：US14162899

申请日：2014-01-24

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Moshe Malkin

IPC: H03M1/10 ,  H04B17/21 ,  H03M1/06 ,  H04L1/00

CPC classification number: H03M1/06 ,  H03M1/1038 ,  H03M1/1215 ,  H04B17/21 ,  H04L1/00

Abstract: Techniques for calibration of high-speed interleaved analog-to-digital converter (ADC) arrays are presented. A transceiver comprises an ADC component that comprises an array of sub-ADCs that can be interleaved to facilitate high-speed data communications. The ADC component processes signals received from a remote transmitter to facilitate recovering the received data. The transceiver can comprise a calibration component that determines transfer characteristics of the communication channel or medium between the transceiver and the remote transmitter, and the transfer characteristics of the remote transmitter to each of the sub-ADCs of the array, based on the recovered data. The calibration component calibrates sub-ADCs of the array to facilitate correcting sub-ADC path differences, based on the respective transfer characteristics, to facilitate mitigating distortions that would be caused by the path differences, wherein the calibration component can use channel estimation to determine the transfer functions of the sub-ADCs of the array.

Abstract translation: 提出了用于校准高速交错模数转换器（ADC）阵列的技术。 收发器包括一个ADC组件，它包括一个可以进行交错以便于高速数据通信的子ADC阵列。 ADC组件处理从远程发射机接收的信号，以便于恢复接收到的数据。 收发器可以包括校准组件，其基于恢复的数据确定收发器和远程发射器之间的通信信道或介质的传输特性以及远程发射机到阵列的每个子ADC的传输特性。 校准组件校准阵列的子ADC以便于基于相应的传输特性校正子ADC路径差异，以便于减轻由路径差引起的失真，其中校准组件可以使用信道估计来确定 阵列的子ADC的传递函数。

公开(公告)号：US20150110233A1

公开(公告)日：2015-04-23

申请号：US14061307

申请日：2013-10-23

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda AZENKOT ,  Timothy P. Walker

IPC: H04L7/033

CPC classification number: H03L7/093 ,  H04J3/07

Abstract: Systems and methods for efficient jitter mitigation or removal from a gapped signal. A phase mitigation module is employed to generate discrete correction values for modifying phase error signals detected between a gapped signal and a feedback signal of the PLL. The correction values can be digitally subtracted from the output of a phase frequency detector associated with the PLL. The sequence of correction values can be determined based on phase frequency differences between the input signal and a targeted feedback signal that is free of jitter and has a period equal to an average period of the input signal. An average of the correction values is substantially equal to zero, and an average of the modified phase error signal is substantially equal to zero.

Abstract translation: 用于有效抖动缓解或从间隙信号中移除的系统和方法。 使用相位缓解模块来产生离散校正值，用于修改在有效信号和PLL的反馈信号之间检测的相位误差信号。 可以从与PLL相关联的相位频率检测器的输出中数字地减去校正值。 校正值的顺序可以基于输入信号和无抖动的目标反馈信号之间的相位差，并且具有等于输入信号的平均周期的周期来确定。 校正值的平均值基本上等于零，并且修正的相位误差信号的平均值基本上等于零。

公开(公告)号：US20150098469A1

公开(公告)日：2015-04-09

申请号：US14045065

申请日：2013-10-03

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Keyur Chudgar ,  Kumar Sankaran

IPC: H04L12/741 ,  H04L29/06 ,  H04L12/863 ,  H04L12/801

CPC classification number: H04L45/74 ,  H04L47/34 ,  H04L47/41 ,  H04L47/50 ,  H04L69/166

Abstract: A system and method are provided for performing transmission control protocol segmentation on a server on a chip using coprocessors on the server chip. A system processor manages the TCP/IP stack and prepares a large (64 KB) single chunk of data to be sent out via a network interface on the server on a chip. The system software processes this and calls the interface device driver to send the packet out. The device driver, instead of sending the packet out directly on the interface, calls a coprocessor interface and delivers some metadata about the chunk of data to the interface. The coprocessor segments the chunk of data into a maximum transmission unit size associated with the network interface and increments a sequential number field in the header information of each packet before sending the segments to the network interface.

Abstract translation: 提供了一种用于在服务器芯片上使用协处理器在芯片上的服务器上执行传输控制协议分段的系统和方法。 系统处理器管理TCP / IP协议栈，并准备通过芯片上的服务器上的网络接口发送的大量（64 KB）单个数据块。 系统软件处理这个并调用接口设备驱动程序发送数据包。 设备驱动程序而不是直接在接口上发送数据包，调用协处理器接口，并将一些关于数据块的元数据传送到接口。 协处理器将数据块划分为与网络接口相关联的最大传输单元大小，并在将段发送到网络接口之前，在每个分组的报头信息中增加序列号字段。

公开(公告)号：US08972806B2

公开(公告)日：2015-03-03

申请号：US13654833

申请日：2012-10-18

Applicant: Applied Micro Circuits Corporation

Inventor： Glen Miller

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/3171 ,  G01R31/31715

Abstract: Providing for testing of digital sequencing components of an integrated chip is described herein. By way of example, self-test procedures are provided for unidirectional integrated chips that have different sequence generation (e.g., transmission) and sequence monitoring (e.g., receiving) frequencies. A test logic component(s) can be added to an integrated chip to match the sequence generation frequency to the sequence monitoring frequency. This can facilitate self-testing of unidirectional sequence generating components, by modifying a generated sequence at a first datarate to be receivable at a second datarate, and directing the modified sequence to sequence monitoring components of the integrated chip configured to operate at the second datarate.

Abstract translation: 本文描述了对集成芯片的数字排序组件的测试。 作为示例，为具有不同序列生成（例如，传输）和序列监视（例如，接收）频率的单向集成芯片提供自检程序。 可以将测试逻辑组件添加到集成芯片以将序列产生频率与序列监视频率相匹配。 这可以通过修改在第二数据位可接收的第一数据位上产生的序列，以及将经修改的序列引导到被配置为在第二数据位上操作的集成芯片的序列监视组件，从而促进单向序列生成组件的自检。

公开(公告)号：US20150032794A1

公开(公告)日：2015-01-29

申请号：US13953059

申请日：2013-07-29

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Millind Mittal ,  Phil Mitchell

IPC: H04L12/819

CPC classification number: H04L47/215 ,  H04L47/2408

Abstract: Provided is an end-to-end flow control management for a system on chip interface. As tokens are injected into agents arranged in a computer network, the input point for the token is dynamically changed such that tokens are not always injected into the same agent. Additionally or alternatively, as tokens are injected into a token ring, the tokens are initially not activated until a predetermined event occurs (e.g., after a specific number of hops). Additionally or alternatively, also provided is a free pool manager that can keep at least some high priority slots available by consuming lower priority slots first.

Abstract translation: 提供了一种用于片上系统接口的端到端流控制管理。 由于令牌被注入到安排在计算机网络中的代理中，令牌的输入点被动态地改变，使得令牌并不总是被注入同一个代理。 附加地或替代地，当令牌被注入到令牌环中时，令牌最初不被激活，直到发生预定事件（例如，在特定数量的跳数之后）。 附加地或替代地，还提供了一个空闲池管理器，其可以首先通过消耗较低优先级时隙来保持至少一些高优先级时隙可用。