公开(公告)号：US20060278341A1

公开(公告)日：2006-12-14

申请号：US11506833

申请日：2006-08-21

Applicant: Jeong-hyuck Park ,  Hee-duk Kim ,  Jung-hun Cho ,  Jong-wook Choi ,  Sung-bum Cho ,  Young-koo Lee ,  Jin-sung Kim ,  Jang-eun Lee ,  Ju-hyuck Chung ,  Sun-hoo Park ,  Jae-hyun Lee ,  Shin-woo Nam

Inventor： Jeong-hyuck Park ,  Hee-duk Kim ,  Jung-hun Cho ,  Jong-wook Choi ,  Sung-bum Cho ,  Young-koo Lee ,  Jin-sung Kim ,  Jang-eun Lee ,  Ju-hyuck Chung ,  Sun-hoo Park ,  Jae-hyun Lee ,  Shin-woo Nam

IPC: H01L21/306

CPC classification number: H01J37/32431 ,  C23C16/4583 ,  C23C16/4585 ,  C23C16/54 ,  H01J37/32623 ,  H01J37/32642 ,  H01L21/32136 ,  H01L21/6831 ,  H01L21/68735 ,  Y10T117/10

Abstract: A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.

公开(公告)号：US20060174473A1

公开(公告)日：2006-08-10

申请号：US11347280

申请日：2006-02-06

Applicant: Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Kyung-Tae Nam ,  Young-Ki Ha

Inventor： Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Kyung-Tae Nam ,  Young-Ki Ha

IPC: G11B5/33 ,  G11B5/127 ,  H04R31/00

CPC classification number: G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3909 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12 ,  Y10T29/49034 ,  Y10T29/49044

Abstract: Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line. A method of forming a semiconductor memory device may include forming a digit line on a substrate, forming an intermediate insulating layer covering the digit line, forming a magnetic tunnel junction (MTJ) pattern on the intermediate insulating layer, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., performing an annealing operation at a temperature of about 350° C. or higher, and forming a bit line connected to the capping pattern and disposed to intersect the digit line.

Abstract translation: 本发明的示例性实施例公开了半导体存储器件和形成存储器件的方法。 半导体存储器件可以包括设置在衬底上的数字线，覆盖数字线的中间绝缘层，设置在中间绝缘层上方和数字线上的磁性隧道结（MTJ）图案，MTJ图案包括顺序堆叠 下磁性图案，上磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上磁性图案反应，而位线连接到封盖图案并且设置成与数字线相交 。 形成半导体存储器件的方法可以包括在衬底上形成数字线，形成覆盖数字线的中间绝缘层，在中间绝缘层上形成磁隧道结（MTJ）图案，MTJ图案包括顺序层叠的 较低的磁性图案，上部磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上部磁性图案反应，在约350℃或更高的温度下进行退火操作， 并且形成连接到所述封盖图案并且设置成与所述数字线相交的位线。

公开(公告)号：US20060027451A1

公开(公告)日：2006-02-09

申请号：US11198725

申请日：2005-08-05

Applicant: Jeong-Hee Park ,  Jang-Eun Lee ,  Sung-Lae Cho

Inventor： Jeong-Hee Park ,  Jang-Eun Lee ,  Sung-Lae Cho

IPC: C23C14/34 ,  C23C14/32

CPC classification number: C23C14/34 ,  C23C14/345 ,  C23C14/35 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625

Abstract: A method of sputtering to deposit a target material onto a substrate includes supplying an ionized gas to the substrate and the target material. A first DC bias voltage having a polarity opposite that of the ionized gas is applied to the target material to attract ions theretoward. A second DC bias voltage having a polarity opposite that of the first DC bias voltage is intermittently applied to the target material to reduce ion accumulation thereon. Related apparatus and methods of fabricating phase-changeable memory devices are also discussed.

Abstract translation: 将目标材料沉积到基板上的溅射方法包括向基板和目标材料供给电离气体。 将具有与电离气体的极性相反的极性的第一DC偏置电压施加到靶材料以向其吸引离子。 具有与第一直流偏置电压相反的极性的第二直流偏置电压被间歇地施加到目标材料上以减少其上的离子积聚。 还讨论了制造相变存储器件的相关装置和方法。

公开(公告)号：US20050263829A1

公开(公告)日：2005-12-01

申请号：US11139283

申请日：2005-05-27

Applicant: Yoon-Jong Song ,  Young-Nam Hwang ,  Sang-Don Nam ,  Sung-Lae Cho ,  Gwan-Hyeob Koh ,  Choong-Man Lee ,  Bong-Jin Kuh ,  Yong-Ho Ha ,  Su-Youn Lee ,  Chang-Wook Jeong ,  Ji-Hye Yi ,  Kyung-Chang Ryoo ,  Se-Ho Lee ,  Su-Jin Ahn ,  Soon-Oh Park ,  Jang-Eun Lee

Inventor： Yoon-Jong Song ,  Young-Nam Hwang ,  Sang-Don Nam ,  Sung-Lae Cho ,  Gwan-Hyeob Koh ,  Choong-Man Lee ,  Bong-Jin Kuh ,  Yong-Ho Ha ,  Su-Youn Lee ,  Chang-Wook Jeong ,  Ji-Hye Yi ,  Kyung-Chang Ryoo ,  Se-Ho Lee ,  Su-Jin Ahn ,  Soon-Oh Park ,  Jang-Eun Lee

IPC: H01L21/00 ,  H01L21/336 ,  H01L27/24 ,  H01L29/00 ,  H01L29/78

CPC classification number: H01L29/7843 ,  H01L27/2436 ,  H01L29/665 ,  H01L29/7833 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1666 ,  H01L45/1675

Abstract: In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.

Abstract translation: 在一个实施例中，相变存储器件具有防止存储器单元污染或氧化的氧化阻挡层及其制造方法。 在一个实施例中，半导体存储器件包括覆盖半导体衬底的成型层。 模制层具有从其顶表面垂直延伸的突出部分。 该装置还包括与突出部分相邻的相变材料图案和与相变材料图案电连接的下部电极。

公开(公告)号：US20050035383A1

公开(公告)日：2005-02-17

申请号：US10851387

申请日：2004-05-24

Applicant: Young-Ki Ha ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Jun-Soo Bae ,  In-Gyu Baek ,  Se-Chung Oh

Inventor： Young-Ki Ha ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Jun-Soo Bae ,  In-Gyu Baek ,  Se-Chung Oh

IPC: G11C11/15 ,  H01F10/32 ,  H01L43/08 ,  H01L29/76

CPC classification number: B82Y25/00 ,  G11C11/15 ,  H01F10/3204 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3295 ,  H01L43/08

Abstract: A magnetic tunnel junction device includes a magnetically programmable free magnetic layer. The free magnetic layer includes a lamination of at least two ferromagnetic layers and at least one intermediate layer interposed between the at least two ferromagnetic layers.

Abstract translation: 磁性隧道结装置包括可磁性可编程的自由磁性层。 自由磁性层包括至少两个铁磁层和至少一个介于至少两个铁磁层之间的中间层的叠层。

公开(公告)号：US08796042B2

公开(公告)日：2014-08-05

申请号：US13286630

申请日：2011-11-01

Applicant: Hee-Ju Shin ,  Jun-Ho Jeong ,  Jang-Eun Lee ,  Se-Chung Oh

Inventor： Hee-Ju Shin ,  Jun-Ho Jeong ,  Jang-Eun Lee ,  Se-Chung Oh

IPC: H01L21/00

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/228

Abstract: A method of fabricating a magnetic tunnel junction structure includes forming a magnetic tunnel junction layer on a substrate. A mask pattern is formed on a region of the second magnetic layer. A magnetic tunnel junction layer pattern and a sidewall dielectric layer pattern on at least one sidewall of the magnetic tunnel junction layer pattern are formed by performing at least one etch process and at least one oxidation process multiple times. The at least one etch process may include a first etch process to etch a portion of the magnetic tunnel junction layer using an inert gas and the mask pattern to form a first etch product. The at least one oxidation process may include a first oxidation process to oxidize the first etch product attached on an etched side of the magnetic tunnel junction layer.

Abstract translation: 制造磁性隧道结结构的方法包括在衬底上形成磁性隧道结层。 在第二磁性层的区域上形成掩模图案。 通过多次执行至少一个蚀刻工艺和至少一个氧化工艺来形成在磁性隧道结层图案的至少一个侧壁上的磁性隧道结层图案和侧壁电介质层图案。 所述至少一个蚀刻工艺可以包括使用惰性气体蚀刻磁性隧道结层的一部分并且掩模图案以形成第一蚀刻产物的第一蚀刻工艺。 所述至少一个氧化工艺可以包括第一氧化工艺以氧化附着在磁性隧道结层的蚀刻侧上的第一蚀刻产物。

公开(公告)号：US08772846B2

公开(公告)日：2014-07-08

申请号：US13398640

申请日：2012-02-16

Applicant: Jeong Heon Park ,  Woo Chang Lim ,  Sechung Oh ,  Young Hyun Kim ,  Sang Hwan Park ,  Jang Eun Lee

Inventor： Jeong Heon Park ,  Woo Chang Lim ,  Sechung Oh ,  Young Hyun Kim ,  Sang Hwan Park ,  Jang Eun Lee

IPC: H01L21/14

CPC classification number: H01L43/08 ,  G06F13/16 ,  G11C11/161 ,  G11C11/1659 ,  H01L43/02 ,  H01L43/10

Abstract: Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures.

Abstract translation: 本发明提供一种包括具有磁性层的第一结构的磁性隧道接合装置; 包括至少两个外在垂直磁化结构的第二结构，每个包括磁性层; 磁性层上的垂直磁化诱导层; 以及第一和第二结构之间的隧道屏障。

公开(公告)号：US08345467B2

公开(公告)日：2013-01-01

申请号：US13219582

申请日：2011-08-26

Applicant: Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

Inventor： Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

IPC: G11C11/00

CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/32 ,  G11C2213/79

Abstract: A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.

Abstract translation: 基于电阻的随机存取存储器（ReRAM）可以包括读出放大器电路，其响应于对第二块的读取操作，包括耦合到ReRAM的第一块中的参考单元的位线的第一输入。

公开(公告)号：US08288289B2

公开(公告)日：2012-10-16

申请号：US13016228

申请日：2011-01-28

Applicant: Jun-Ho Jeong ,  Jang-Eun Lee ,  Se-Chung Oh ,  Suk-Hun Choi ,  Jea-Hyoung Lee ,  Woo-Jin Kim ,  Woo-Chang Lim

Inventor： Jun-Ho Jeong ,  Jang-Eun Lee ,  Se-Chung Oh ,  Suk-Hun Choi ,  Jea-Hyoung Lee ,  Woo-Jin Kim ,  Woo-Chang Lim

IPC: H01L21/302

CPC classification number: H01L21/28

Abstract: A method of fabricating a semiconductor device, the method including providing a substrate; forming an underlying layer on the substrate; forming a sacrificial layer on the underlying layer; forming an opening in the sacrificial layer by patterning the sacrificial layer such that the opening exposes a predetermined region of the underlying layer; forming a mask layer in the opening; forming an oxide mask by partially or completely oxidizing the mask layer; removing the sacrificial layer; and etching the underlying layer using the oxide mask as an etch mask to form an underlying layer pattern.

Abstract translation: 一种制造半导体器件的方法，所述方法包括提供衬底; 在衬底上形成下层; 在下层上形成牺牲层; 通过图案化所述牺牲层在所述牺牲层中形成开口，使得所述开口暴露所述下层的预定区域; 在开口中形成掩模层; 通过部分或完全氧化掩模层形成氧化物掩模; 去除牺牲层; 并使用氧化物掩模作为蚀刻掩模蚀刻下层以形成下层图案。

公开(公告)号：US07838863B2

公开(公告)日：2010-11-23

申请号：US12388707

申请日：2009-02-19

Applicant: Jin-Shi Zhao ,  Jang-Eun Lee ,  In-Gyu Baek ,  Hyun-Jun Sim ,  Xiang-Shu Li ,  Eun-Kyung Yim

Inventor： Jin-Shi Zhao ,  Jang-Eun Lee ,  In-Gyu Baek ,  Hyun-Jun Sim ,  Xiang-Shu Li ,  Eun-Kyung Yim

IPC: H01L29/02

CPC classification number: G11C13/02 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/101 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147

Abstract: Provided is a semiconductor device including a resistive memory element. The semiconductor device includes a substrate and the resistive memory element disposed on the substrate. The resistive memory element has resistance states of a plurality of levels according to generation and dissipation of at least one platinum bridge therein.

Abstract translation: 提供了包括电阻式存储元件的半导体器件。 半导体器件包括衬底和设置在衬底上的电阻性存储元件。 根据其中至少一个铂桥的产生和耗散，电阻性存储元件具有多个电平的电阻状态。