公开(公告)号：US06975032B2

公开(公告)日：2005-12-13

申请号：US10319967

申请日：2002-12-16

Applicant: Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

Inventor： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

公开(公告)号：US20050001325A1

公开(公告)日：2005-01-06

申请号：US10611931

申请日：2003-07-03

Applicant: Panayotis Andricacos ,  Shyng-Tsong Chen ,  John Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe Vereecken

Inventor： Panayotis Andricacos ,  Shyng-Tsong Chen ,  John Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe Vereecken

IPC: H01L21/00 ,  H01L21/288 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76846 ,  H01L21/2885 ,  H01L21/6708 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76874 ,  H01L21/76883

Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

Abstract translation: 通过在衬垫材料的存在下使用选择性蚀刻和/或选择性电镀选择性地封盖铜来制造图案化的铜结构。 提供了用于解决在电蚀和/或电镀过程中作为电解质增加的电阻路径从晶片边缘向内流动的问题的装置。

公开(公告)号：US06756624B2

公开(公告)日：2004-06-29

申请号：US10409010

申请日：2003-04-07

Applicant: Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

Inventor： Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

IPC: H01L27108

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/7684 ,  H01L28/60

Abstract: A method is described for fabricating an encapsulated metal structure in a feature formed in a substrate. The sidewalls and bottom of the feature are covered by a barrier layer and the feature is filled with metal, preferably by electroplating. A recess is formed in the metal, and an additional barrier layer is deposited, covering the top surface of the metal and contacting the first barrier layer. The additional barrier layer is planarized, preferably by chemical-mechanical polishing. The method may be used in fabricating a MIM capacitor, with the encapsulated metal structure serving as the lower plate of the capacitor. A second substrate layer is deposited on the top surface of the substrate, with an opening overlying the encapsulated metal structure. A dielectric layer is deposited in the opening, covering the encapsulated metal structure at the bottom thereof. An additional layer, serving as the upper plate of the capacitor, is deposited to cover the dielectric layer and to fill the opening. The dielectric layer and the additional layer are planarized, preferably by CMP.

Abstract translation: 描述了一种在衬底中形成的特征中制造封装金属结构的方法。 特征的侧壁和底部被阻挡层覆盖，并且该特征被金属填充，优选地通过电镀。 在金属中形成凹部，并且沉积附加的阻挡层，覆盖金属的顶表面并与第一阻挡层接触。 优选通过化学机械抛光将附加阻挡层平坦化。 该方法可用于制造MIM电容器，其中封装的金属结构用作电容器的下板。 第二衬底层沉积在衬底的顶表面上，具有覆盖封装的金属结构的开口。 介电层沉积在开口中，覆盖其底部的封装金属结构。 作为电容器的上板的附加层被沉积以覆盖电介质层并填充开口。 介电层和附加层优选通过CMP平坦化。

公开(公告)号：US06656369B2

公开(公告)日：2003-12-02

申请号：US10053314

申请日：2002-01-17

Applicant: Mahadevaiyer Krishnan ,  Mark E. Lagus ,  Kevin S. Petrarca ,  James G. Ryan ,  Richard P. Volant

Inventor： Mahadevaiyer Krishnan ,  Mark E. Lagus ,  Kevin S. Petrarca ,  James G. Ryan ,  Richard P. Volant

IPC: B44C122

CPC classification number: G01Q70/16

Abstract: A scanning probe microscope probe is formed by depositing probe material in a mold that has a cavity in a shape and of a size of the desired form of the scanning probe microscope probe that is being fabricated. In the preferred embodiment, the cavity is formed by lithographically defining, in the body of the mold, the shape and the size of the desired scanning probe microscope probe and etching the body of the mold to form the cavity. Prior to depositing the probe material in the cavity in the mold, the cavity is lined with a release layer which, upon activation after the probe has been formed, permits removal of the probe.

Abstract translation: 扫描探针显微镜探针通过将探针材料沉积在具有正在制造的扫描探针显微镜探针的所需形状和尺寸的空腔的模具中而形成。 在优选实施例中，通过在模具主体中光刻地限定所需扫描探针显微镜探针的形状和尺寸并蚀刻模具主体以形成空腔而形成空腔。 在将探针材料沉积在模具中的空腔中之前，空腔内衬有释放层，其在探针已经形成之后激活，允许去除探针。

公开(公告)号：US06597068B2

公开(公告)日：2003-07-22

申请号：US10034862

申请日：2001-12-28

Applicant: Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

Inventor： Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

IPC: H01L2348

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/7684 ,  H01L28/60

Abstract: A method is described for fabricating an encapsulated metal structure in a feature formed in a substrate. The sidewalls and bottom of the feature are covered by a barrier layer and the feature is filled with metal, preferably by electroplating. A recess is formed in the metal, and an additional barrier layer is deposited, covering the top surface of the metal and contacting the first barrier layer. The additional barrier layer is planarized, preferably by chemical-mechanical polishing. The method may be used in fabricating a MIM capacitor, with the encapsulated metal structure serving as the lower plate of the capacitor. A second substrate layer is deposited on the top surface of the substrate, with an opening overlying the encapsulated metal structure. A dielectric layer is deposited in the opening, covering the encapsulated metal structure at the bottom thereof. An additional layer, serving as the upper plate of the capacitor, is deposited to cover the dielectric layer and to fill the opening. The dielectric layer and the additional layer are planarized, preferably by CMP.

公开(公告)号：US06503834B1

公开(公告)日：2003-01-07

申请号：US09677585

申请日：2000-10-03

Applicant: Xiaomeng Chen ,  Mahadevaiyer Krishnan ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  Soon-Cheon Seo ,  James A. Tornello

Inventor： Xiaomeng Chen ,  Mahadevaiyer Krishnan ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  Soon-Cheon Seo ,  James A. Tornello

IPC: H01L2144

CPC classification number: H01L21/76849 ,  H01L21/288

Abstract: The invention provides a process to increase the reliability of BEOL interconnects. The process comprises forming an array of conductors on a dielectric layer on a wafer substrate, polishing the upper surface so that the surfaces of the conductors are substantially co-planar with the upper surface of the dielectric layer, forming an alloy film on the upper surfaces of the conductors, and brush cleaning the upper surfaces of the conductors and the dielectric layer.

Abstract translation: 本发明提供了增加BEOL互连的可靠性的过程。 该方法包括在晶片衬底上的电介质层上形成导体阵列，抛光上表面，使得导体的表面与电介质层的上表面基本上共面，在上表面上形成合金膜 的导体，并刷清洁导体和电介质层的上表面。

公开(公告)号：US06368953B1

公开(公告)日：2002-04-09

申请号：US09567466

申请日：2000-05-09

Applicant: Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

Inventor： Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

IPC: H01L214763

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/7684 ,  H01L28/60

Abstract: A method is described for fabricating an encapsulated metal structure in a feature formed in a substrate. The sidewalls and bottom of the feature are covered by a barrier layer and the feature is filled with metal, preferably by electroplating. A recess is formed in the metal, and an additional barrier layer is deposited, covering the top surface of the metal and contacting the first barrier layer. The additional barrier layer is planarized, preferably by chemical-mechanical polishing. The method may be used in fabricating a MIM capacitor, with the encapsulated metal structure serving as the lower plate of the capacitor. A second substrate layer is deposited on the top surface of the substrate, with an opening overlying the encapsulated metal structure. A dielectric layer is deposited in the opening, covering the encapsulated metal structure at the bottom thereof. An additional layer, serving as the upper plate of the capacitor, is deposited to cover the dielectric layer and to fill the opening. The dielectric layer and the additional layer are planarized, preferably by CMP.

Abstract translation: 描述了一种在衬底中形成的特征中制造封装金属结构的方法。 特征的侧壁和底部被阻挡层覆盖，并且该特征被金属填充，优选地通过电镀。 在金属中形成凹部，并且沉积附加的阻挡层，覆盖金属的顶表面并与第一阻挡层接触。 优选通过化学机械抛光将附加阻挡层平坦化。 该方法可用于制造MIM电容器，其中封装的金属结构用作电容器的下板。 第二衬底层沉积在衬底的顶表面上，具有覆盖封装的金属结构的开口。 介电层沉积在开口中，覆盖其底部的封装金属结构。 作为电容器的上板的附加层被沉积以覆盖电介质层并填充开口。 介电层和附加层优选通过CMP平坦化。

公开(公告)号：US06153935A

公开(公告)日：2000-11-28

申请号：US409244

申请日：1999-09-30

Applicant: Daniel C. Edelstein ,  Timothy J. Dalton ,  John G. Gaudiello ,  Mahadevaiyer Krishnan ,  Sandra G. Malhotra ,  Maurice McGlashan-Powell ,  Eugene J. O'Sullivan ,  Carlos J. Sambucetti

Inventor： Daniel C. Edelstein ,  Timothy J. Dalton ,  John G. Gaudiello ,  Mahadevaiyer Krishnan ,  Sandra G. Malhotra ,  Maurice McGlashan-Powell ,  Eugene J. O'Sullivan ,  Carlos J. Sambucetti

IPC: H01L21/30 ,  H01L21/288 ,  H01L21/321 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76849 ,  H01L21/288 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76835

Abstract: A damascene interconnect containing a dual etch stop/diffusion barrier. The conductive material of the damascene interconnect is capped with a conductive metal diffusion barrier cap, typically using electroless deposition, and, optionally, with a dielectric etch-stop layer. An optional chemical mechanical polish-stop layer may also be present. The different methods of the invention allow the CMP stop, reactive-ion etch stop, and metal diffusion barrier requirements of the different layers to be decoupled. A preferred conductive material is copper.

Abstract translation: 包含双蚀刻停止/扩散屏障的镶嵌互连。 镶嵌互连的导电材料用导电金属扩散阻挡盖（通常使用无电沉积）和可选地与电介质蚀刻停止层封盖。 还可以存在任选的化学机械抛光 - 停止层。 本发明的不同方法允许不同层的CMP停止，反应离子蚀刻停止和金属扩散阻挡层要求被去耦合。 优选的导电材料是铜。

公开(公告)号：US5635253A

公开(公告)日：1997-06-03

申请号：US487808

申请日：1995-06-07

Applicant: Donald F. Canaperi ,  Rangarajan Jagannathan ,  Mahadevaiyer Krishnan

Inventor： Donald F. Canaperi ,  Rangarajan Jagannathan ,  Mahadevaiyer Krishnan

IPC: C23C18/31 ,  C23C18/16 ,  C23C18/44 ,  B32B17/10

CPC classification number: C23C18/1617

Abstract: A replenishing solution for a cyanide-based electroless gold plating bath. The solution includes a gold(III) halide such as gold chloride, gold bromide, tetrachloroaurate (and its sodium, potassium, and ammonium salts), and tetrabromoaurate (and its sodium, potassium, and ammonium salts). The replenishing solution also may include an alkali (such as potassium hydroxide, sodium hydroxide, and ammonium hydroxide) to maintain the pH of the solution between 8 and 14. Also provided is a method of replenishing a cyanide-based electroless gold plating bath with the solution of the present invention.

Abstract translation: 一种基于氰化物的无电镀金液的补充溶液。 该溶液包括金（III）卤化物如氯化金，溴化金，四氯牛磺酸盐（及其钠盐，钾盐和铵盐）和四溴乙酸盐（及其钠盐，钾盐和铵盐）。 补充溶液还可以包括碱（例如氢氧化钾，氢氧化钠和氢氧化铵），以保持溶液的pH在8和14之间。还提供了一种补充基于氰化物的无电镀金浴的方法， 本发明的溶液。

公开(公告)号：US5102456A

公开(公告)日：1992-04-07

申请号：US618769

申请日：1990-11-27

Applicant: Rangarajan Jagannathan ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Gregory P. Wandy

Inventor： Rangarajan Jagannathan ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Gregory P. Wandy

IPC: C23C18/40

CPC classification number: C23C18/40 ,  Y10T428/12694 ,  Y10T428/12903 ,  Y10T428/31681

Abstract: An electroless copper plating bath uses a series of tetradentate nitrogen ligands. The components of the bath may be substituted without extensive re-optimization of the bath. The Cu-tetra-aza ligand baths operates over a pH range between 7 and 12. Stable bath formulations employing various buffers, reducing agents and ligands have been developed. The process can be used for metal deposition at lower pH and provides the capability to use additive processing for metallization in the presence of polyimide, positive photoresist and other alkali sensitive substrates.

Abstract translation: 化学镀铜浴使用一系列四齿氮配体。 浴的组分可以被代替而没有大量重新优化浴。 Cu-四氮杂配体浴在7和12之间的pH范围内运行。已经开发了使用各种缓冲液，还原剂和配体的稳定浴配方。 该方法可用于较低pH下的金属沉积，并提供在聚酰亚胺，正性光致抗蚀剂和其他碱敏感基材存在下使用添加剂处理进行金属化的能力。