公开(公告)号：US20060284271A1

公开(公告)日：2006-12-21

申请号：US11158621

申请日：2005-06-21

Applicant: Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Matthew Mertz ,  Mark Doczy ,  Suman Datta ,  Robert Chau

Inventor： Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Matthew Mertz ,  Mark Doczy ,  Suman Datta ,  Robert Chau

IPC: H01L29/94

CPC classification number: H01L29/4983 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28247 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66628

Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions.

公开(公告)号：US07122870B2

公开(公告)日：2006-10-17

申请号：US10916191

申请日：2004-08-09

Applicant: John Barnak ,  Collin Borla ,  Mark Doczy ,  Markus Kuhn ,  Jacob M. Jensen

Inventor： John Barnak ,  Collin Borla ,  Mark Doczy ,  Markus Kuhn ,  Jacob M. Jensen

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H02L31/113

CPC classification number: H01L21/28088 ,  H01L29/4966

Abstract: A method of forming a gate electrode is described, comprising forming a dielectric layer on a substrate, forming a first metal layer having a first work function on the dielectric layer, forming a second metal layer having a second work function on the first metal layer, such that a gate electrode is formed on the dielectric layer which has a work function that is determined from the work function of the alloy of the two types of metal. The work function of a microelectronic transistor can be varied or “tuned” depending on the precise definition and control of the metal types, layer sequence, individual layer thickness and total number of layers.

Abstract translation: 描述了形成栅电极的方法，包括在基片上形成电介质层，在介电层上形成具有第一功函数的第一金属层，在第一金属层上形成具有第二功函数的第二金属层， 使得在电介质层上形成栅电极，其具有由两种类型的金属的合金的功函数确定的功函数。 微电子晶体管的功能可以根据金属类型，层序列，单层厚度和总层数的精确定义和控制而变化或“调谐”。

公开(公告)号：US20060186484A1

公开(公告)日：2006-08-24

申请号：US11064996

申请日：2005-02-23

Applicant: Robert Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz

Inventor： Robert Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US20060180878A1

公开(公告)日：2006-08-17

申请号：US11393151

申请日：2006-03-29

Applicant: Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Annalisa Cappellani ,  Robert Chau

Inventor： Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Annalisa Cappellani ,  Robert Chau

IPC: H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/82345 ,  H01L21/28229 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.

公开(公告)号：US20060160371A1

公开(公告)日：2006-07-20

申请号：US11037644

申请日：2005-01-18

Applicant: Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

Inventor： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC: H01L21/31

CPC classification number: H01L21/28194 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02304 ,  H01L21/28079 ,  H01L21/3141 ,  H01L21/31691 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: Oxidation between a higher dielectric constant material such as a rare earth oxide and a substrate may be reduced by providing a seal layer over the gate dielectric. In some embodiments, the seal layer may be isolated from the gate dielectric by a buffer layer.

Abstract translation: 通过在栅极电介质上设置密封层，可以减少较高介电常数材料如稀土氧化物与基底之间的氧化。 在一些实施例中，密封层可以通过缓冲层与栅极电介质隔离。

公开(公告)号：US20060157747A1

公开(公告)日：2006-07-20

申请号：US11037512

申请日：2005-01-18

Applicant: Amlan Majumdar ,  Justin Brask ,  Marko Radosavljevic ,  Suman Datta ,  Brian Doyle ,  Mark Doczy ,  Jack Kavalieros ,  Matthew Metz ,  Robert Chau ,  Uday Shah ,  James Blackwell

Inventor： Amlan Majumdar ,  Justin Brask ,  Marko Radosavljevic ,  Suman Datta ,  Brian Doyle ,  Mark Doczy ,  Jack Kavalieros ,  Matthew Metz ,  Robert Chau ,  Uday Shah ,  James Blackwell

IPC: H01L29/76

CPC classification number: B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1606 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0541 ,  H01L51/0545 ,  Y10S977/701 ,  Y10S977/938

Abstract: A nanotube transistor, such as a carbon nanotube transistor, may be formed with a top gate electrode and a spaced source and drain. Conduction along the transistor from source to drain is controlled by the gate electrode. Underlying the gate electrode are at least two nanotubes. In some embodiments, the substrate may act as a back gate.

Abstract translation: 诸如碳纳米管晶体管的纳米管晶体管可以形成有顶栅电极和间隔开的源极和漏极。 沿晶体管从源极到漏极的导通由栅电极控制。 栅电极底部至少有两个纳米管。 在一些实施例中，衬底可用作背栅。

公开(公告)号：US20060138552A1

公开(公告)日：2006-06-29

申请号：US11360269

申请日：2006-02-22

Applicant: Justin Brask ,  Brian Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

Inventor： Justin Brask ,  Brian Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Uday Shah ,  Robert Chau

IPC: H01L29/94

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US20060081932A1

公开(公告)日：2006-04-20

申请号：US11292911

申请日：2005-12-01

Applicant: Been-Yih Jin ,  Brian Doyle ,  Scott Hareland ,  Mark Doczy ,  Matthew Metz ,  Boyan Boyanov ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

Inventor： Been-Yih Jin ,  Brian Doyle ,  Scott Hareland ,  Mark Doczy ,  Matthew Metz ,  Boyan Boyanov ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

IPC: H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78681

Abstract: A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.

公开(公告)号：US20060065939A1

公开(公告)日：2006-03-30

申请号：US10951073

申请日：2004-09-27

Applicant: Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Robert Chau

Inventor： Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Chris Barns ,  Matthew Metz ,  Suman Datta ,  Robert Chau

IPC: H01L29/94 ,  H01L21/3205

CPC classification number: H01L21/823437 ,  H01L21/823828

Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with NMOS and PMOS transistors that have high dielectric constant gate dielectric material over a semiconductor substrate. A metal barrier layer may be formed over the gate dielectric. A workfunction setting metal layer is formed over the metal barrier layer and a cap metal layer is formed over the workfunction setting metal layer.

Abstract translation: 互补金属氧化物半导体集成电路可以形成有在半导体衬底上具有高介电常数栅极电介质材料的NMOS和PMOS晶体管。 可以在栅极电介质上方形成金属阻挡层。 在金属阻挡层上方形成功函设定金属层，在功函设定金属层上形成帽金属层。

公开(公告)号：US20060063318A1

公开(公告)日：2006-03-23

申请号：US10938778

申请日：2004-09-10

Applicant: Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Marko Radosavljevic ,  Amlan Majumdar ,  Justin Brask ,  Robert Chau

Inventor： Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Marko Radosavljevic ,  Amlan Majumdar ,  Justin Brask ,  Robert Chau

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L51/102 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0545 ,  H01L51/105

Abstract: Ambipolar conduction can be reduced in carbon nanotube transistors by forming a gate electrode of a metal. Metal sidewall spacers having different workfunctions than the gate electrode may be formed to bracket the metal gate electrode.

Abstract translation: 通过形成金属的栅电极，可以在碳纳米管晶体管中减少双极传导。 可以形成具有与栅电极不同的功函数的金属侧壁间隔物以支撑金属栅电极。