公开(公告)号：US06849509B2

公开(公告)日：2005-02-01

申请号：US10315646

申请日：2002-12-09

申请人： John Barnak ,  Collin Borla ,  Mark Doczy ,  Markus Kuhn ,  Jacob M. Jensen

发明人： John Barnak ,  Collin Borla ,  Mark Doczy ,  Markus Kuhn ,  Jacob M. Jensen

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/8234

CPC分类号： H01L21/28088 ,  H01L29/4966

摘要： A method of forming a gate electrode is described, comprising forming a dielectric layer on a substrate, forming a first metal layer having a first work function on the dielectric layer, forming a second metal layer having a second work function on the first metal layer, such that a gate electrode is formed on the dielectric layer which has a work function that is determined from the work function of the alloy of the two types of metal. The work function of a microelectronic transistor can be varied or “tuned” depending on the precise definition and control of the metal types, layer sequence, individual layer thickness and total number of layers.

摘要翻译： 描述了形成栅电极的方法，包括在基片上形成电介质层，在介电层上形成具有第一功函数的第一金属层，在第一金属层上形成具有第二功函数的第二金属层， 使得在电介质层上形成栅电极，其具有由两种类型的金属的合金的功函数确定的功函数。 微电子晶体管的功能可以根据金属类型，层序列，单层厚度和总层数的精确定义和控制而变化或“调谐”。

公开(公告)号：US07122870B2

公开(公告)日：2006-10-17

申请号：US10916191

申请日：2004-08-09

申请人： John Barnak ,  Collin Borla ,  Mark Doczy ,  Markus Kuhn ,  Jacob M. Jensen

发明人： John Barnak ,  Collin Borla ,  Mark Doczy ,  Markus Kuhn ,  Jacob M. Jensen

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H02L31/113

CPC分类号： H01L21/28088 ,  H01L29/4966

摘要： A method of forming a gate electrode is described, comprising forming a dielectric layer on a substrate, forming a first metal layer having a first work function on the dielectric layer, forming a second metal layer having a second work function on the first metal layer, such that a gate electrode is formed on the dielectric layer which has a work function that is determined from the work function of the alloy of the two types of metal. The work function of a microelectronic transistor can be varied or “tuned” depending on the precise definition and control of the metal types, layer sequence, individual layer thickness and total number of layers.

摘要翻译： 描述了形成栅电极的方法，包括在基片上形成电介质层，在介电层上形成具有第一功函数的第一金属层，在第一金属层上形成具有第二功函数的第二金属层， 使得在电介质层上形成栅电极，其具有由两种类型的金属的合金的功函数确定的功函数。 微电子晶体管的功能可以根据金属类型，层序列，单层厚度和总层数的精确定义和控制而变化或“调谐”。

公开(公告)号：US20050009311A1

公开(公告)日：2005-01-13

申请号：US10916191

申请日：2004-08-09

申请人： John Barnak ,  Collin Borla ,  Mark Doczy ,  Markus Kuhn ,  Jacob Jensen

发明人： John Barnak ,  Collin Borla ,  Mark Doczy ,  Markus Kuhn ,  Jacob Jensen

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/8238

CPC分类号： H01L21/28088 ,  H01L29/4966

摘要： A method of forming a gate electrode is described, comprising forming a dielectric layer on a substrate, forming a first metal layer having a first work function on the dielectric layer, forming a second metal layer having a second work function on the first metal layer, such that a gate electrode is formed on the dielectric layer which has a work function that is determined from the work function of the alloy of the two types of metal. The work function of a microelectronic transistor can be varied or “tuned” depending on the precise definition and control of the metal types, layer sequence, individual layer thickness and total number of layers.

公开(公告)号：US20050045961A1

公开(公告)日：2005-03-03

申请号：US10652350

申请日：2003-08-29

申请人： John Barnak ,  Mark Doczy ,  Robert Chau ,  Collin Borla

发明人： John Barnak ,  Mark Doczy ,  Robert Chau ,  Collin Borla

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L29/76

CPC分类号： H01L21/28194 ,  H01L29/513 ,  H01L29/518

摘要： A technique for producing an enhanced gate structure having a silicon-nitride buffer. Embodiments relate to the structure and development of a gate structure having a silicon-nitride buffer layer deposited upon a dielectric layer, upon which a gate material, such as polysilicon, is deposited.

公开(公告)号：US20050233530A1

公开(公告)日：2005-10-20

申请号：US11154747

申请日：2005-06-15

申请人： John Barnak ,  Mark Doczy ,  Robert Chau ,  Collin Borla

发明人： John Barnak ,  Mark Doczy ,  Robert Chau ,  Collin Borla

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/28194 ,  H01L29/513 ,  H01L29/518

摘要： A technique for producing an enhanced gate structure having a silicon-nitride buffer. Embodiments relate to the structure and development of a gate structure having a silicon-nitride buffer layer deposited upon a dielectric layer, upon which a gate material, such as polysilicon, is deposited.

摘要翻译： 一种用于制造具有氮化硅缓冲液的增强栅极结构的技术。 实施例涉及具有沉积在电介质层上的氮化硅缓冲层的栅极结构的结构和发展，其上沉积诸如多晶硅的栅极材料。

公开(公告)号：US20050026451A1

公开(公告)日：2005-02-03

申请号：US10632470

申请日：2003-08-01

申请人： Justin Brask ,  Mark Doczy ,  Matthew Metz ,  John Barnak ,  Paul Markworth

发明人： Justin Brask ,  Mark Doczy ,  Matthew Metz ,  John Barnak ,  Paul Markworth

IPC分类号： H01L21/3063 ,  H01L21/28 ,  H01L21/311 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/28123 ,  H01L21/31111

摘要： A high-K thin film patterning solution is disclosed to address structural and process limitations of conventional patterning techniques. Subsequent to formation of gate structures adjacent a high-K dielectric layer, a portion of the high-K dielectric layer material is reduced, preferably via exposure to hydrogen gas, to form a reduced portion of the high-K dielectric layer. The reduced portion may be selectively removed utilizing wet etch chemistries to leave behind a trench of desirable geometric properties.

摘要翻译： 公开了一种高K薄膜图形解决方案，以解决常规图案化技术的结构和工艺限制。 在与高K电介质层相邻形成栅极结构之后，优选通过暴露于氢气来降低高K电介质层材料的一部分，以形成高K电介质层的减少的部分。 可以使用湿蚀刻化学物质选择性地去除还原部分，以留下所需几何性质的沟槽。

公开(公告)号：US20050017238A1

公开(公告)日：2005-01-27

申请号：US10626336

申请日：2003-07-24

申请人： Justin Brask ,  Mark Doczy ,  John Barnak

发明人： Justin Brask ,  Mark Doczy ,  John Barnak

IPC分类号： H01L21/316 ,  H01L29/12

CPC分类号： H01L21/02323 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/02343 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31683

摘要： A liquid form oxidizer may be utilized to form a high dielectric constant dielectric material from a metallic precursor for semiconductor applications. The use of a liquid rather than a gaseous oxidizer reduces the presence of an oxidation under layer under the metallic precursor. It may also, in some embodiments, result in a purer dielectric film.

摘要翻译： 可以使用液体形式氧化剂从用于半导体应用的金属前体形成高介电常数电介质材料。 液体而不是气态氧化剂的使用减少了在金属前体下面氧化层的存在。 在一些实施例中，也可以产生更纯的电介质膜。

公开(公告)号：US20050110072A1

公开(公告)日：2005-05-26

申请号：US11018015

申请日：2004-12-20

申请人： Justin Brask ,  Mark Doczy ,  Matthew Metz ,  John Barnak ,  Paul Markworth

发明人： Justin Brask ,  Mark Doczy ,  Matthew Metz ,  John Barnak ,  Paul Markworth

IPC分类号： H01L21/3063 ,  H01L21/28 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/76

CPC分类号： H01L21/28123 ,  H01L21/31111

摘要： A high-K thin film patterning solution is disclosed to address structural and process limitations of conventional patterning techniques. Subsequent to formation of gate structures adjacent a high-K dielectric layer, a portion of the high-K dielectric layer material is reduced, preferably via exposure to hydrogen gas, to form a reduced portion of the high-K dielectric layer. The reduced portion may be selectively removed utilizing wet etch chemistries to leave behind a trench of desirable geometric properties.

公开(公告)号：US20050048794A1

公开(公告)日：2005-03-03

申请号：US10652796

申请日：2003-08-28

申请人： Justin Brask ,  Mark Doczy ,  Scott Hareland ,  John Barnak ,  Matthew Metz ,  Jack Kavalieros ,  Robert Chau

发明人： Justin Brask ,  Mark Doczy ,  Scott Hareland ,  John Barnak ,  Matthew Metz ,  Jack Kavalieros ,  Robert Chau

IPC分类号： H01L21/28 ,  H01L21/30 ,  H01L21/306 ,  H01L21/316 ,  H01L29/51 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02244 ,  H01L21/02052 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/3003 ,  H01L21/31612 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31683 ,  H01L21/31691 ,  H01L29/513 ,  H01L29/517

摘要： A method for making a semiconductor device is described. That method comprises forming a metal oxide layer on a substrate, converting at least part of the metal oxide layer to a metal layer; and oxidizing the metal layer to generate a metal oxide high-k gate dielectric layer.

公开(公告)号：US20060030104A1

公开(公告)日：2006-02-09

申请号：US11248737

申请日：2005-10-11

申请人： Mark Doczy ,  Justin Brask ,  Steven Keating ,  Chris Barns ,  Brian Doyle ,  Michael McSwiney ,  Jack Kavalieros ,  John Barnak

发明人： Mark Doczy ,  Justin Brask ,  Steven Keating ,  Chris Barns ,  Brian Doyle ,  Michael McSwiney ,  Jack Kavalieros ,  John Barnak

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7833 ,  Y10S438/926

摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

摘要翻译： 至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。 更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。