公开(公告)号：US08912890B2

公开(公告)日：2014-12-16

申请号：US13632745

申请日：2012-10-01

Applicant: Patrick Smith ,  Criswell Choi ,  James Montague Cleeves ,  Vivek Subramanian ,  Arvind Kamath ,  Steven Molesa

Inventor： Patrick Smith ,  Criswell Choi ,  James Montague Cleeves ,  Vivek Subramanian ,  Arvind Kamath ,  Steven Molesa

IPC: H04Q5/22

CPC classification number: H01G4/40 ,  H01G4/38

Abstract: The disclosure relates to surveillance and/or identification devices having capacitors connected in parallel or in series, and methods of making and using such devices. Devices with capacitors connected in parallel, where one capacitor is fabricated with a relatively thick capacitor dielectric and another is fabricated with a relatively thin capacitor dielectric achieve both a high-precision capacitance and a low breakdown voltage for relatively easy surveillance tag deactivation. Devices with capacitors connected in series result in increased lateral dimensions of a small capacitor. This makes the capacitor easier to fabricate using techniques that may have relatively limited resolution capabilities.

Abstract translation: 本公开涉及具有并联或串联连接的电容器的监视和/或识别装置以及制造和使用这些装置的方法。 具有并联连接电容器的器件，其中一个电容器用相对较厚的电容器电介质制造，另一个电容器由相对薄的电容器电介质制成，实现了高精度电容和低击穿电压，以便相对容易的监视标签去激活。 具有串联连接的电容器的装置增加了小电容器的横向尺寸。 这使得使用可能具有相对有限的分辨能力的技术来制造电容器更容易。

公开(公告)号：US08471308B2

公开(公告)日：2013-06-25

申请号：US13047627

申请日：2011-03-14

Applicant: Vivek Subramanian ,  Patrick Smith

Inventor： Vivek Subramanian ,  Patrick Smith

IPC: H01L29/76

CPC classification number: H01L29/86 ,  H01L27/1285 ,  H01L27/1288 ,  H01L27/1292 ,  Y10S257/91 ,  Y10T307/964

Abstract: Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (Vt) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the Vt of an NMOS TFT (Vtn) and the Vt of a PMOS TFT (Vtp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.

Abstract translation: 公开了包含这种二极管和TFT的工艺变容二极管和二极管连接的薄膜晶体管（TFT），印刷或图案化结构（例如电路），其制造方法及其用于识别标签和传感器的应用。 包括串联的互补二极管或二极管连接的TFT的图案化结构可以稳定使用印刷或激光写入技术制造的二极管的阈值电压（Vt）。 本发明有利地利用NMOS TFT（Vtn）的Vt和PMOS TFT（Vtp）的Vt之间的间隔来建立和/或提高印刷或激光写入的二极管上的正向压降的稳定性。 本发明的其它应用涉及参考电压发生器，电压钳位电路，控制相关或差分信号传输线上的电压的方法，以及RFID和EAS标签和传感器。

公开(公告)号：US07879781B2

公开(公告)日：2011-02-01

申请号：US12465176

申请日：2009-05-13

Applicant: Rajesh Patel ,  Vivek Subramanian ,  Kathleen Combs

Inventor： Rajesh Patel ,  Vivek Subramanian ,  Kathleen Combs

IPC: A61K7/50

CPC classification number: A61K8/342 ,  A61K8/0295 ,  A61K8/31 ,  A61K8/361 ,  A61K8/375 ,  A61K8/922 ,  A61Q19/10

Abstract: The invention comprises a liquid lamellar composition comprising surfactant, a specific lamellar structuring system, emollient, and specific structurant.

Abstract translation: 本发明包括一种液体层状组合物，其包含表面活性剂，特定的层状结构体系，润肤剂和特定的结构剂。

公开(公告)号：US07825455B2

公开(公告)日：2010-11-02

申请号：US12320351

申请日：2009-01-23

Applicant: Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Mark G. Johnson ,  Paul M. Farmwald ,  Igor G. Kouznetsov

Inventor： Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Mark G. Johnson ,  Paul M. Farmwald ,  Igor G. Kouznetsov

IPC: H01L29/788

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract translation: 提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

公开(公告)号：US07659236B2

公开(公告)日：2010-02-09

申请号：US11736871

申请日：2007-04-18

Applicant: Christine Marie Nixon Lee ,  Michael Augustine Brennan ,  Vivek Subramanian

Inventor： Christine Marie Nixon Lee ,  Michael Augustine Brennan ,  Vivek Subramanian

IPC: A61K7/00

CPC classification number: C11D9/444 ,  C11D1/02 ,  C11D1/38 ,  C11D1/65 ,  C11D1/66 ,  C11D1/83 ,  C11D1/835 ,  C11D1/86 ,  C11D3/40 ,  C11D9/267 ,  C11D17/0047 ,  C11D17/006

Abstract: The invention relates to bar compositions comprising thermochromatic pigment or dye signaling temperature and/or benefit agent release. In a preferred embodiment, the pigment is introduced in the form of a separate domain (e.g., separate chips) which separate chip or chips is combined with a surfactant-containing chips to form the final bar.

Abstract translation: 本发明涉及包含热色素或染料信号传导温度和/或有益剂释放的棒组合物。 在一个优选的实施方案中，将颜料以单独的区域（例如分离的芯片）的形式引入，其将芯片或芯片与含表面活性剂的芯片组合以形成最终的棒。

公开(公告)号：US20090173985A1

公开(公告)日：2009-07-09

申请号：US12320351

申请日：2009-01-23

Applicant: Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Andrew J. Walker ,  Christopher J. Peti ,  Igor G. Kouznetzov ,  Mark G. Johnson ,  Paul Michael Farmwald

Inventor： Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Andrew J. Walker ,  Christopher J. Peti ,  Igor G. Kouznetzov ,  Mark G. Johnson ,  Paul Michael Farmwald

IPC: H01L29/792 ,  H01L29/788

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract translation: 提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

公开(公告)号：US07528017B2

公开(公告)日：2009-05-05

申请号：US11521924

申请日：2006-09-15

Applicant: Vivek Subramanian ,  Patrick Smith

Inventor： Vivek Subramanian ,  Patrick Smith

IPC: H01L21/20

CPC classification number: H01L29/86 ,  H01L27/1285 ,  H01L27/1288 ,  H01L27/1292 ,  Y10S257/91 ,  Y10T307/964

Abstract: Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (Vt) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the Vt of an NMOS TFT (Vtn) and the Vt of a PMOS TFT (Vtp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.

Abstract translation: 公开了包含这种二极管和TFT的工艺变容二极管和二极管连接的薄膜晶体管（TFT），印刷或图案化结构（例如电路），其制造方法及其用于识别标签和传感器的应用。 包括串联的互补二极管或二极管连接的TFT的图案化结构可以稳定使用印刷或激光写入技术制造的二极管的阈值电压（Vt）。 本发明有利地利用NMOS TFT（Vtn）的Vt和PMOS TFT（Vtp）的Vt之间的间隔来建立和/或提高印刷或激光写入的二极管上的正向压降的稳定性。 本发明的其它应用涉及参考电压发生器，电压钳位电路，控制相关或差分信号传输线上的电压的方法，以及RFID和EAS标签和传感器。

公开(公告)号：US07319053B2

公开(公告)日：2008-01-15

申请号：US11355214

申请日：2006-02-14

Applicant: Vivek Subramanian ,  James M. Cleeves

Inventor： Vivek Subramanian ,  James M. Cleeves

IPC: H01L21/82

CPC classification number: G11C17/06 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/16

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract translation: 公开了一种非常高密度的现场可编程存储器。 阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。 自动对准技术的最大限度地使光刻限制最小化。 在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

公开(公告)号：US07160761B2

公开(公告)日：2007-01-09

申请号：US10251206

申请日：2002-09-19

Applicant: James M. Cleeves ,  Vivek Subramanian

Inventor： James M. Cleeves ,  Vivek Subramanian

IPC: H01L21/82

CPC classification number: G11C17/06 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/16

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

公开(公告)号：US07071565B2

公开(公告)日：2006-07-04

申请号：US10255884

申请日：2002-09-26

Applicant: Calvin K. Li ,  N. Johan Knall ,  Michael A. Vyvoda ,  James M. Cleeves ,  Vivek Subramanian

Inventor： Calvin K. Li ,  N. Johan Knall ,  Michael A. Vyvoda ,  James M. Cleeves ,  Vivek Subramanian

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  G11C8/00

CPC classification number: H01L27/0688 ,  H01L21/32135 ,  H01L21/8221 ,  H01L27/1214 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three dimensional circuit structure including tapered pillars between first and second signal lines. An apparatus including a first plurality of spaced apart coplanar conductors disposed in a first plane over a substrate; a second plurality of spaced apart coplanar conductors disposed in a second plane, the second plane parallel to and different from the first plane; and a plurality of cells disposed between one of the first conductors and one of the second conductors, wherein each of the plurality of cells have a re-entrant profile.