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725 条记录 (耗时 0.031 秒)

    Method for making a design layout and mask
    61.
    再颁专利
    Method for making a design layout and mask 有权
    制作设计布局和面具的方法

    公开(公告)号：USRE42302E1

    公开(公告)日：2011-04-19

    申请号：US11905862

    申请日：2007-10-04

    申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

    发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

    IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F11/22

    CPC分类号： G06F17/5081

    摘要： A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.

    摘要翻译： 提供了一种用于设计半导体集成电路的方法，其包括基于给定的设计规则压缩半导体集成电路的设计布局以获得压缩图案，预测在用于形成的晶片的表面区域形成的图案 所述半导体集成电路基于所述压实图案，通过将所述预测图案与所述压实图案进行比较来获得评价值，判定所述评价值是否满足预定条件，以及当所述评价值被判定为不满足时修改所述设计规则 预定条件。

    Radio frequency (RF) power amplifier and RF power amplifier apparatus
    62.
    发明授权
    Radio frequency (RF) power amplifier and RF power amplifier apparatus 有权
    射频（RF）功率放大器和RF功率放大器装置

    公开(公告)号：US07876156B2

    公开(公告)日：2011-01-25

    申请号：US12412728

    申请日：2009-03-27

    申请人： Satoshi Tanaka ,  Tomonori Tanoue

    发明人： Satoshi Tanaka ,  Tomonori Tanoue

    IPC分类号： H03G3/30

    CPC分类号： H03F3/19 ,  H03F1/0261 ,  H03F3/245 ,  H03F2200/393 ,  H03F2200/451

    摘要： An RF power amplifier has a final-stage amplifier stage which generates an RF transmit output signal, a signal detector which detects an RF transmit output level, a first detector, a second detector and a control circuit. The final-stage amplifier stage includes a transistor and a load element and performs saturation type nonlinear amplification and non-saturation type linear amplification. The first detector and the control circuit maintain the RF transmit output signal approximately constant with respect to a variation in load at an antenna at the saturation type nonlinear amplification. The second detector and the control circuit reduce an increase in the output voltage of the final stage transistor with respect to an overload state of the antenna at the non-saturation type linear amplification.

    摘要翻译： RF功率放大器具有产生RF发射输出信号的最终级放大器级，检测RF发射输出电平的信号检测器，第一检测器，第二检测器和控制电路。 最后一级放大器级包括晶体管和负载元件，并执行饱和型非线性放大和非饱和型线性放大。 第一检测器和控制电路保持RF发射输出信号相对于饱和型非线性放大在天线处的负载变化大致恒定。 第二检测器和控制电路在非饱和型线性放大时相对于天线的过载状态减小了最终级晶体管的输出电压的增加。

    Fan Drive Controlling Device and Construction Machine
    64.
    发明申请
    Fan Drive Controlling Device and Construction Machine 审中-公开
    风机驱动控制装置及施工机械

    公开(公告)号：US20110011356A1

    公开(公告)日：2011-01-20

    申请号：US12934016

    申请日：2009-03-18

    申请人： Satoshi Tanaka ,  Kizuki Hagiwara

    发明人： Satoshi Tanaka ,  Kizuki Hagiwara

    IPC分类号： F01P7/04 ,  F04D27/00

    CPC分类号： F04D25/022 ,  E02F9/2228 ,  E02F9/2235 ,  E02F9/226 ,  E02F9/2292 ,  E02F9/2296 ,  F01P7/046 ,  F01P2025/06 ,  F01P2025/60 ,  F04D25/04 ,  F04D27/004 ,  F15B2211/20546 ,  F15B2211/31576 ,  F15B2211/45 ,  F15B2211/5157 ,  F15B2211/633 ,  F15B2211/6343

    摘要： A fan drive control device includes: a hydraulic motor driving a cooling fan by a hydraulic oil supplied from a hydraulic pump driven by an engine; a flow rate adjuster adjusting a flow rate of the hydraulic oil flowed into the hydraulic motor; a temperature sensor detecting a temperature of a fluid cooled by a cooling fan; an accelerator pedal angle sensor detecting an accelerator pedal angle for controlling an engine power based on a detected value by the temperature sensor; a target flow rate setting unit setting a target flow rate of the hydraulic oil flowed into the hydraulic motor; a target flow rate compensation unit compensating the target flow rate based on a detected value by the accelerator pedal angle sensor; and a control command generator generating a control command to the flow rate adjuster according to the target flow rate by the target flow rate compensation unit.

    摘要翻译： 一种风扇驱动控制装置，包括：液压马达，其由从由发动机驱动的液压泵供给的液压油驱动冷却风扇; 流量调节器，其调节流入所述液压马达的液压油的流量; 检测由冷却风扇冷却的流体的温度的温度传感器; 加速器踏板角度传感器，其基于所述温度传感器的检测值，检测用于控制发动机功率的加速器踏板角; 目标流量设定单元，设定流入所述液压马达的所述液压油的目标流量; 目标流量补偿单元，基于加速器踏板角度传感器的检测值补偿目标流量; 以及控制命令生成器，其通过目标流量补偿单元根据目标流量向流量调节器生成控制命令。

    Semiconductor memory
    67.
    发明授权
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号：US07847363B2

    公开(公告)日：2010-12-07

    申请号：US12370638

    申请日：2009-02-13

    申请人： Kikuko Sugimae ,  Satoshi Tanaka ,  Koji Hashimoto ,  Masayuki Ichige

    发明人： Kikuko Sugimae ,  Satoshi Tanaka ,  Koji Hashimoto ,  Masayuki Ichige

    IPC分类号： G11C5/00

    CPC分类号： G11C5/063 ,  G11C16/0408 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531

    摘要： Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi+1, . . . , AAn, which extend on a memory cell array along the column length; a plurality of word line patterns WL1, WL2, . . . , extend along the row length and are non-uniformly arranged; a plurality of select gate line patterns SG1, SG2, . . . , are arranged parallel to the plurality of word line patterns; borderless contacts are formed near the ends of the word line patterns on the memory cell array, and are in contact with part of an interconnect extended from the end of the memory cell array, but are not in contact with interconnects adjacent to that interconnect; and bit line contacts are formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.

    摘要翻译： 用于字线的无边界触点或通过位线的触点使用互连图案形成，其中一部分被去除。 半导体存储器包括：多个有源区域AAi，AAi + 1，...， 。 。 ，AAn，其沿着列长延伸在存储单元阵列上; 多个字线图案WL1，WL2，...。 。 。 沿着行长延伸并且不均匀地布置; 多个选择栅极线图案SG1，SG2，...。 。 。 被平行于所述多个字线图形排列; 在存储单元阵列上的字线图案的端部附近形成无边界触点，并且与从存储单元阵列的端部延伸的互连部分接触，但不与与该互连件相邻的互连件接触; 并且通过去除多个字线图案的一部分而提供的接触形成区域内形成位线接触，并通过双重曝光选择栅极线图案。

    Plasma processing method and plasma processing apparatus
    68.
    发明授权
    Plasma processing method and plasma processing apparatus 有权
    等离子体处理方法和等离子体处理装置

    公开(公告)号：US07829463B2

    公开(公告)日：2010-11-09

    申请号：US11694126

    申请日：2007-03-30

    申请人： Naoki Matsumoto ,  Chishio Koshimizu ,  Manabu Iwata ,  Satoshi Tanaka

    发明人： Naoki Matsumoto ,  Chishio Koshimizu ,  Manabu Iwata ,  Satoshi Tanaka

    IPC分类号： H01L21/44

    CPC分类号： H01L21/31116 ,  H01J37/32091 ,  H01J37/32174 ,  H01J37/32623 ,  H01J37/32706 ,  H01J37/32935

    摘要： A plasma processing method performs a desired plasma process on substrates by using a plasma generated in a processing space. A first and a second electrode are disposed in parallel in a processing vessel that is grounded, the substrate is supported on the second electrode to face the first electrode, the processing vessel is vacuum evacuated, a desired processing gas is supplied into the processing space formed between the first electrode, the second electrode and a sidewall of the processing vessel, and a first radio frequency power is supplied to the second electrode. The first electrode is connected to the processing vessel via an insulator or a space, and is electrically coupled to a ground potential via a capacitance varying unit whose electrostatic capacitance is varied based on a process condition of the plasma process performed on the substrate.

    摘要翻译： 等离子体处理方法通过使用在处理空间中产生的等离子体在衬底上进行所需的等离子体处理。 第一电极和第二电极平行放置在接地的处理容器中，基板被支撑在第二电极上以面对第一电极，处理容器被真空抽真空，所需的处理气体被供应到形成的处理空间 在第一电极，第二电极和处理容器的侧壁之间，并且向第二电极提供第一射频功率。 第一电极经由绝缘体或空间连接到处理容器，并且经由静电电容根据在衬底上进行的等离子体处理的工艺条件而变化的电容变化单元电耦合到接地电位。

    Semiconductor device pattern creation method, pattern data processing method, pattern data processing program, and semiconductor device manufacturing method
    69.
    发明申请
    Semiconductor device pattern creation method, pattern data processing method, pattern data processing program, and semiconductor device manufacturing method 审中-公开
    半导体器件图案生成方法，图案数据处理方法，图案数据处理程序和半导体器件制造方法

    公开(公告)号：US20100275174A1

    公开(公告)日：2010-10-28

    申请号：US12801895

    申请日：2010-06-30

    申请人： Ayako Nakano ,  Satoshi Tanaka ,  Toshiya Kotani

    发明人： Ayako Nakano ,  Satoshi Tanaka ,  Toshiya Kotani

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G03F1/36

    摘要： A correction target pattern having a size not more than a threshold value is extracted from first design data containing a pattern of a semiconductor integrated circuit. The first characteristic of the semiconductor integrated circuit is calculated on the basis of the first design data. Second design data is generated by correcting the correction target pattern contained in the first design data. The second characteristic of the semiconductor integrated circuit is calculated on the basis of the second design data. It is checked whether the characteristic difference between the first characteristic and the second characteristic falls within a tolerance. It is decided to use the second design data to manufacture the semiconductor integrated circuit when the characteristic difference falls within the tolerance.

    摘要翻译： 从包含半导体集成电路的图案的第一设计数据中提取尺寸不大于阈值的校正对象图案。 基于第一设计数据计算半导体集成电路的第一特性。 通过校正包含在第一设计数据中的校正目标图案来生成第二设计数据。 基于第二设计数据计算半导体集成电路的第二特性。 检查第一特性和第二特性之间的特性差是否落在公差之内。 当特性差在公差范围内时，决定使用第二设计数据来制造半导体集成电路。