公开(公告)号：US08431470B2

公开(公告)日：2013-04-30

申请号：US13079675

申请日：2011-04-04

申请人： Sik Lui ,  Yi Su ,  Daniel Ng ,  Anup Bhalla

发明人： Sik Lui ,  Yi Su ,  Daniel Ng ,  Anup Bhalla

IPC分类号： H01L21/28 ,  H01L21/02

CPC分类号： H01L29/7806 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.

摘要翻译： 集成结构结合了场效应晶体管和肖特基二极管。 形成衬底组合物的沟槽沿其中形成台面的衬底组合物的深度延伸。 每个沟槽填充有导电材料，该导电材料通过形成栅极区域的电介质材料与沟槽壁分离。 每个台面形状内部的两个第一导电类型体区部分地沉积到基底组合物的深度中。 衬底组合物的暴露部分分离身体区域。 每个身体区域内的第二导电类型源区域与每个孔的相邻侧和相邻侧相邻。 每个孔内的肖特基势垒金属在分离体区的基底组合物的暴露部分的暴露的垂直侧壁的界面处形成肖特基结。

公开(公告)号：US20120248530A1

公开(公告)日：2012-10-04

申请号：US13079675

申请日：2011-04-04

申请人： Sik Lui ,  Yi Su ,  Daniel Ng ,  Anup Bhalla

发明人： Sik Lui ,  Yi Su ,  Daniel Ng ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L29/872 ,  H01L21/8234

CPC分类号： H01L29/7806 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.

摘要翻译： 集成结构结合了场效应晶体管和肖特基二极管。 形成衬底组合物的沟槽沿其中形成台面的衬底组合物的深度延伸。 每个沟槽填充有导电材料，该导电材料通过形成栅极区域的电介质材料与沟槽壁分离。 每个台面形状内部的两个第一导电类型体区部分地沉积到基底组合物的深度中。 衬底组合物的暴露部分分离身体区域。 每个身体区域内的第二导电类型源区域与每个孔的相邻侧和相邻侧相邻。 每个孔内的肖特基势垒金属在分离体区的基底组合物的暴露部分的暴露的垂直侧壁的界面处形成肖特基结。

公开(公告)号：US20120199875A1

公开(公告)日：2012-08-09

申请号：US13020758

申请日：2011-02-03

申请人： Anup Bhalla ,  Sik Lui ,  Jun Hu ,  Fei Wang

发明人： Anup Bhalla ,  Sik Lui ,  Jun Hu ,  Fei Wang

IPC分类号： H01L27/085

CPC分类号： H03K17/6871 ,  H01L27/0629 ,  H01L27/085 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H03K17/0406 ,  H03K17/102 ,  H03K17/567 ,  H03K2017/6875 ,  H01L2924/00

摘要： A switching device includes a low voltage normally-off transistor and a control circuit built into a common die. The device includes source, gate and drain electrodes for the transistor and one or more auxiliary electrodes. The drain electrode is on one surface of a die on which the transistor is formed, while each of the remaining electrodes is located on an opposite surface. The one or more auxiliary electrodes provide electrical contact to the control circuit, which is electrically connected to one or more of the other electrodes.

摘要翻译： 开关器件包括低电压常关晶体管和内置在公共管芯中的控制电路。 该器件包括用于晶体管的源极，栅极和漏极以及一个或多个辅助电极。 漏电极在其上形成晶体管的管芯的一个表面上，而每个剩余的电极位于相对的表面上。 一个或多个辅助电极提供与控制电路的电接触，该电接触电连接到一个或多个其它电极。

公开(公告)号：US20120193676A1

公开(公告)日：2012-08-02

申请号：US12931429

申请日：2011-01-31

申请人： Madhur Bobde ,  Harsh Naik ,  Lingpeng Guan ,  Anup Bhalla ,  Sik Lui

发明人： Madhur Bobde ,  Harsh Naik ,  Lingpeng Guan ,  Anup Bhalla ,  Sik Lui

IPC分类号： H01L29/72 ,  H01L21/331

CPC分类号： H01L29/7391

摘要： This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体器件。 半导体器件包括在第一主表面上的第一导电类型的第一半导体层。 半导体器件还包括在与第一主表面相对的第二主表面上的第二导电类型的第二半导体层。 该半导体器件还包括设置在第二半导体层正下方的第一导电类型的注入效率控制缓冲层，以控制第二半导体层的注入效率。

公开(公告)号：US20120146090A1

公开(公告)日：2012-06-14

申请号：US12968179

申请日：2010-12-14

申请人： Sik Lui ,  Anup Bhalla

发明人： Sik Lui ,  Anup Bhalla

IPC分类号： H01L29/739 ,  H01L21/28 ,  H01L21/331

CPC分类号： H01L29/7397 ,  H01L21/76877 ,  H01L21/7688 ,  H01L27/0635 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66704 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8613 ,  H01L29/872

摘要： Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact.

摘要翻译： 晶体管器件可以使用自对准的集成二极管制造。 该器件包括掺杂半导体衬底，其具有形成在衬底中的沟槽中的一个或多个电绝缘栅电极。 一个或多个主体区域形成在靠近每个栅极沟槽的衬底的顶部。 一个或多个源极区域以自对准方式形成在靠近每个栅极沟槽的主体区域的顶部部分中。 在基板的顶表面上的栅电极上形成一个或多个厚的绝缘体部分，在相邻的厚绝缘体部分之间具有间隔。 在厚的绝缘体部分上的衬底的顶部上形成金属。 金属通过厚的绝缘体部分之间的空间形成与衬底的自对准接触。 在自对准接触下形成集成二极管。

公开(公告)号：US20110049580A1

公开(公告)日：2011-03-03

申请号：US12550230

申请日：2009-08-28

申请人： Sik Lui ,  Anup Bhalla

发明人： Sik Lui ,  Anup Bhalla

IPC分类号： H01L27/088 ,  H01L21/98 ,  H01L23/52

CPC分类号： H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/50 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107 ,  H03K17/567 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A hybrid packaged gate controlled semiconductor switching device (HPSD) has an insulated-gate transistor (IGT) made of a first semiconductor die and a rectifying-gate transistor (RGT) made of a second semiconductor die. The RGT gate and source are electrically connected to the IGT source and drain respectively. The HPSD includes a package base with package terminals for interconnecting the HPSD to external environment. The IGT is die bonded atop the package base. The second semiconductor die is formed upon a composite semiconductor epi layer overlaying an electrically insulating substrate (EIS) thus creating a RGT die. The RGT die is stacked and bonded atop the IGT die via the EIS. The IGT, RGT die and package terminals are interconnected with bonding wires. Thus, the HPSD is a stacked package of IGT die and RGT die with reduced package footprint while allowing flexible placements of device terminal electrodes on the IGT.

摘要翻译： 混合封装的栅极控制半导体开关器件（HPSD）具有由第一半导体管芯和由第二半导体管芯制成的整流栅晶体管（RGT）制成的绝缘栅晶体管（IGT）。 RGT栅极和源极分别电连接到IGT源极和漏极。 HPSD包括一个具有封装端子的封装基座，用于将HPSD与外部环境相互连接。 IGT被封装在封装基座的顶部。 第二半导体管芯形成在覆盖电绝缘衬底（EIS）的复合半导体外延层上，从而产生RGT管芯。 RGT芯片通过EIS堆叠并粘合在IGT管芯的顶部。 IGT，RGT管芯和封装端子与接合线互连。 因此，HPSD是IGT芯片和RGT裸片的堆叠封装，具有减小的封装占地面积，同时允许IGT上的器件端子电极的灵活布置。

公开(公告)号：US07868381B1

公开(公告)日：2011-01-11

申请号：US11982906

申请日：2007-11-05

申请人： Anup Bhalla ,  Domon Pitzer ,  Jacek Korec ,  Xiaorong Shi ,  Sik Lui

发明人： Anup Bhalla ,  Domon Pitzer ,  Jacek Korec ,  Xiaorong Shi ,  Sik Lui

IPC分类号： H01L27/108

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/8725 ,  H01L2924/0002 ,  Y10S257/905 ,  H01L2924/00

摘要： In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

摘要翻译： 在沟槽栅极MIS器件中，沟槽内的栅极接触，从而不需要使栅极材料（通常为多晶硅）延伸到沟槽外部。 这避免了沟槽上角处的应力问题。 栅极金属和多晶硅之间的接触通常在位于器件的有源区域之外的栅极金属区域中形成。 描述了用于形成栅极金属和多晶硅之间的接触的各种构造，包括其中沟槽在接触区域中变宽的实施例。 由于在整个器件中多晶硅被回蚀到硅的顶表面之下，通常不需要多晶硅掩模，从而节省制造成本。

公开(公告)号：US07605425B2

公开(公告)日：2009-10-20

申请号：US11900616

申请日：2007-09-11

申请人： Anup Bhalla ,  Sik Lui ,  Tiesheng Li

发明人： Anup Bhalla ,  Sik Lui ,  Tiesheng Li

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

摘要： A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall.

摘要翻译： 半导体器件包括漏极，设置在漏极上的主体，具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中;延伸穿过源和主体的栅沟槽， 漏极，设置在栅极沟槽中的栅极，具有沟槽壁的源体接触沟槽和沿着沟槽壁布置的抗穿孔植入物。

公开(公告)号：US20060249785A1

公开(公告)日：2006-11-09

申请号：US11125506

申请日：2005-05-09

申请人： Anup Bhalla ,  Daniel Ng ,  Tiesheng Li ,  Sik Lui

发明人： Anup Bhalla ,  Daniel Ng ,  Tiesheng Li ,  Sik Lui

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66712 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7827

摘要： This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

摘要翻译： 本发明公开了一种支撑在半导体上的新开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的所述半导体的第二表面附近的源极区域。 开关装置还包括设置在第二表面顶部的用于控制源极到漏极电流的绝缘栅电极。 开关装置还包括插入到绝缘栅电极中的源电极，用于基本上防止栅电极和绝缘栅电极下方的外延区之间的电场的耦合。 源电极进一步覆盖并延伸在绝缘栅上，以覆盖半导体的第二表面上的区域以接触源区。 半导体衬底还包括设置在漏极区以上且具有与漏极区不同的掺杂浓度的外延层。 绝缘栅电极还包括用于使栅电极与源电极绝缘的绝缘层，其中绝缘层的厚度取决于垂直功率器件的Vgsmax等级。

公开(公告)号：US20060220107A1

公开(公告)日：2006-10-05

申请号：US11182918

申请日：2005-07-14

申请人： Sik Lui ,  Anup Bhalla

发明人： Sik Lui ,  Anup Bhalla

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/7803 ,  H01L29/945 ,  H01L2223/6644 ,  H03K17/165

摘要： This invention discloses a new trenched vertical semiconductor power device that includes a capacitor formed between a conductive layer covering over an inter-dielectric layer disposed on top of a trenched gate. In a specific embodiment, the trenched vertical semiconductor power device may be a trenched metal oxide semiconductor field effect transistor (MOSFET) power device. The trenched gate is a trenched polysilicon gate and the conductive layer is a second polysilicon layer covering an inter-poly dielectric layer disposed on top of the trenched polysilicon gate. The conductive layer is further connected to a source of the vertical power device.

摘要翻译： 本发明公开了一种新的沟槽垂直半导体功率器件，其包括形成在覆盖在沟槽栅极顶部的介电层之间的导电层之间的电容器。 在具体实施例中，沟槽垂直半导体功率器件可以是沟槽金属氧化物半导体场效应晶体管（MOSFET）功率器件。 沟槽栅极是沟槽多晶硅栅极，并且导电层是覆盖设置在沟槽多晶硅栅极顶部的多晶硅介电层的第二多晶硅层。 导电层还连接到垂直功率器件的源极。