公开(公告)号：US10276688B2

公开(公告)日：2019-04-30

申请号：US15896983

申请日：2018-02-14

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Zhiyuan Ye ,  Flora Fong-Song Chang ,  Abhishek Dube ,  Xuebin Li ,  Errol Antonio C. Sanchez ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167 ,  H01L29/417 ,  H01L21/02

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

公开(公告)号：US10125415B2

公开(公告)日：2018-11-13

申请号：US15668026

申请日：2017-08-03

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan Ye ,  Errol Antonio C. Sanchez ,  Keun-Yong Ban ,  Xinyu Bao

IPC: H01L21/02 ,  C23C8/02

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

公开(公告)号：US09925569B2

公开(公告)日：2018-03-27

申请号：US14010025

申请日：2013-08-26

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan Ye

IPC: H01J37/32 ,  B08B5/00 ,  B08B7/00 ,  C23C16/44 ,  C11D11/00 ,  C11D7/02 ,  C11D7/22

CPC classification number: B08B7/005 ,  C11D7/02 ,  C11D7/22 ,  C11D11/0041 ,  C11D11/007 ,  C23C16/4405 ,  H01J37/32522 ,  H01J37/32816 ,  H01J37/32853 ,  H01J37/32862

Abstract: Methods for conditioning interior surfaces of a process chamber are provided herein. In one embodiment a method of conditioning interior surfaces of a process chamber is provided. The method comprises maintaining a process chamber at a first pressure and at a first temperature of less than about 800 degrees Celsius, providing a process gas to the process chamber at the first pressure and the first temperature, wherein the process gas comprises chlorine (Cl2) and high IR absorption gas, and exposing the process gas to radiant energy to remove residue disposed on interior surfaces of the process chamber.

公开(公告)号：US09923081B1

公开(公告)日：2018-03-20

申请号：US15479091

申请日：2017-04-04

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Zhiyuan Ye ,  Flora Fong-Song Chang ,  Abhishek Dube ,  Xuebin Li ,  Errol Antonio C. Sanchez ,  Hua Chung ,  Schubert S. Chu

IPC: H01L23/48 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167

CPC classification number: H01L29/6659 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7851

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

公开(公告)号：US09845550B2

公开(公告)日：2017-12-19

申请号：US14613186

申请日：2015-02-03

Applicant: Applied Materials, Inc.

Inventor： Paul Brillhart ,  Anzhong Chang ,  Edric Tong ,  Kin Pong Lo ,  James Francis Mack ,  Zhiyuan Ye ,  Kartik Shah ,  Errol Antonio C. Sanchez ,  David K. Carlson ,  Satheesh Kuppurao ,  Joseph M. Ranish

IPC: C30B25/14 ,  C30B25/08 ,  C30B25/10 ,  H01L21/67

CPC classification number: C30B25/14 ,  C30B25/08 ,  C30B25/10 ,  H01L21/67115

Abstract: Embodiments provided herein generally relate to an apparatus for delivering gas to a semiconductor processing chamber. An upper quartz dome of an epitaxial semiconductor processing chamber has a plurality of holes formed therein and precursor gases are provided into a processing volume of the chamber through the holes of the upper dome. Gas delivery tubes extend from the holes in the dome to a flange plate where the tubes are coupled to gas delivery lines. The gas delivery apparatus enables gases to be delivered to the processing volume above a substrate through the quartz upper dome.

公开(公告)号：US09159554B2

公开(公告)日：2015-10-13

申请号：US14262400

申请日：2014-04-25

Applicant: Applied Materials, Inc.

Inventor： Errol Antonio C. Sanchez ,  Xinyu Bao ,  Wonseok Lee ,  David Keith Carlson ,  Zhiyuan Ye

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/02546 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/762

Abstract: Embodiments described herein generally relate to a method of fabrication of a device structure comprising Group III-V elements on a substrate. A surface may be formed on a substrate and a Group III-V material may be grown from the surface to form a Group III-V device structure in a trench isolated between a dielectric layer. A final critical dimension of the device structure may be trimmed to achieve a suitably sized node structure.

Abstract translation: 本文描述的实施例通常涉及在衬底上制造包含III-V族元素的器件结构的方法。 可以在衬底上形成A 111表面，并且可以从III族表面生长III-V族材料，以在介电层之间隔离的沟槽中形成III-V族器件结构。 可以修剪设备结构的最终关键尺寸以实现适当尺寸的节点结构。