公开(公告)号：US07365364B2

公开(公告)日：2008-04-29

申请号：US11162135

申请日：2005-08-30

申请人： Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Yi Chang

发明人： Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Yi Chang

IPC分类号： H01L29/267 ,  H01L29/22

CPC分类号： H01L27/14683 ,  H01L27/14618 ,  H01L2224/24226

摘要： A sensor semiconductor device and a method for fabricating the same are proposed. A sensor chip is mounted on a substrate, and a dielectric layer and a circuit layer are formed on the substrate, wherein the circuit layer is electrically connected to the substrate and the sensor chip. The dielectric layer is formed with an opening for exposing a sensor region of the sensor chip. A light-penetrable lid covers the opening of the dielectric layer, such that light is able to penetrate the light-penetrable lid to reach the sensor region and activate the sensor chip. The sensor chip can be electrically connected to an external device via a plurality of solder balls implanted on a surface of the substrate not for mounting the sensor chip. Therefore, the sensor semiconductor device is fabricated in a cost-effective manner, and circuit cracking and a know good die (KGD) problem are prevented.

摘要翻译： 提出了一种传感器半导体器件及其制造方法。 传感器芯片安装在基板上，并且在基板上形成电介质层和电路层，其中电路层电连接到基板和传感器芯片。 电介质层形成有用于暴露传感器芯片的传感器区域的开口。 透光盖子覆盖电介质层的开口，使得光线能够穿透透光盖子到达传感器区域并激活传感器芯片。 传感器芯片可以通过植入在基板的表面上的多个焊球电连接到外部设备，而不用于安装传感器芯片。 因此，传感器半导体器件以成本有效的方式制造，并且防止了电路破裂和知道的裸芯片（KGD）问题。

公开(公告)号：US07354796B2

公开(公告)日：2008-04-08

申请号：US11821269

申请日：2007-06-22

申请人： Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC分类号： H01L21/00

CPC分类号： H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/81801 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

摘要翻译： 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

公开(公告)号：US20070278701A1

公开(公告)日：2007-12-06

申请号：US11591800

申请日：2006-11-01

申请人： Cheng-Yi Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Chieh-Yuan Lin ,  Cheng-Hsu Hsiao

发明人： Cheng-Yi Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Chieh-Yuan Lin ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/28

CPC分类号： H01L21/561 ,  H01L21/481 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a method for fabricating the same are disclosed. The method includes installing a plurality of conductive components on a plurality of chip carriers of a chip carrier module, connecting electrically the conductive components to electrical connection points of the adjacent chip carriers, mounting and electrically connecting a semiconductor chip to each of the chip carries, forming an encapsulant for enveloping the semiconductor chip and the conductive components, cutting the chip carriers to separate the conductive components installed thereon, exposing a portion of the conductive components out of the encapsulant, forming on the exposed portion of the conductive components an electroplated layer of nickel/gold, and separating the chip carriers from each other. The conductive components exposed out of the encapsulant provide extra electrical connection points and thereby promote the functionalities of electronic products.

摘要翻译： 公开了一种半导体封装及其制造方法。 该方法包括在芯片载体模块的多个芯片载体上安装多个导电组件，将导电组件电连接到相邻芯片载体的电连接点，将半导体芯片安装并电连接到每个芯片载体， 形成用于包封半导体芯片和导电部件的密封剂，切割芯片载体以分离安装在其上的导电组件，将一部分导电组分暴露于密封剂外，在导电组件的暴露部分上形成电镀层 镍/金，并且将芯片载体彼此分离。 从密封剂露出的导电组件提供额外的电连接点，从而促进电子产品的功能。

公开(公告)号：US07170152B2

公开(公告)日：2007-01-30

申请号：US10846460

申请日：2004-05-14

申请人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

IPC分类号： H01L23/02

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00

摘要： A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.

摘要翻译： 提供具有积层的晶片级半导体封装，其包括具有用于接收其中的半导体芯片的通孔的玻璃框架，填充在形成在半导体芯片和玻璃框架之间的空间内的低模量缓冲材料， 形成在所述玻璃框架和所述半导体芯片上的堆积层，使得所述积层层电连接到所述半导体芯片，以及安装在所述积层层上的多个导电元件，使得所述半导体芯片电连接 到外部设备。 通过使用玻璃框架和低模量缓冲材料，由此获得的晶片级半导体封装没有翘曲，芯片裂纹和分层问题，并且其可靠性得到提高。 还提供了一种用于制造晶片级半导体封装的方法。

公开(公告)号：US07005720B2

公开(公告)日：2006-02-28

申请号：US10763656

申请日：2004-01-23

申请人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L31/0203 ,  H01L27/14618 ,  H01L2224/04042 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor package with a photosensitive chip and a fabrication method thereof are provided. A substrate having a core is prepared. A solder mask layer is applied over a surface of the core and formed with an opening to expose a continuous peripheral portion on the surface of the core. At least one photosensitive chip is mounted on and electrically connected to the substrate. An encapsulation dam is formed on the continuous peripheral portion of the core and surrounds the chip. The dam includes a shoulder portion adjacent to and flush with the solder mask layer, and a protruded support portion surrounding the shoulder portion. A lid is attached to the support portion of the dam for sealing the dam such that the chip is received in a space defined by the substrate, the dam and the lid.

摘要翻译： 提供具有感光芯片的半导体封装及其制造方法。 制备具有芯的衬底。 将焊接掩模层施加在芯的表面上并形成有开口以暴露芯的表面上的连续周边部分。 至少一个感光芯片安装在基板上并与其电连接。 在芯的连续外围部分上形成封装坝，并围绕芯片。 大坝包括与焊料掩模层相邻并与其齐平的肩部，以及围绕肩部的突出的支撑部。 盖子附接到坝的支撑部分，用于密封坝，使得芯片被容纳在由基板，坝和盖子限定的空间中。

公开(公告)号：US20050212129A1

公开(公告)日：2005-09-29

申请号：US10974293

申请日：2004-10-26

申请人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

IPC分类号： H01L21/44 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L23/52 ,  H01L23/538

CPC分类号： H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor package with a build-up structure is provided, which includes a rigid base, a rigid frame having a through hole and fixed onto the rigid base, at least one chip received in the through hole of the rigid frame, a medium filled in a gap between the chip and the rigid frame, a build-up structure formed on the chip and the rigid frame and electrically connected to the chip, and a plurality of conductive elements bonded to the build-up structure to electrically connect the chip to external devices. The use of the rigid base and rigid frame can avoid structural warpage, cracking, delamination and a popcorn effect of the semiconductor package. A method for fabricating the semiconductor package is also provided.

摘要翻译： 提供具有积聚结构的半导体封装，其包括刚性基座，具有通孔并固定到刚性基座上的刚性框架，容纳在刚性框架的通孔中的至少一个芯片，填充在 芯片和刚性框架之间的间隙，形成在芯片上的积聚结构和刚性框架并电连接到芯片，以及多个导电元件，其结合到构建结构以将芯片电连接到外部 设备。 使用刚性基体和刚性框架可以避免半导体封装的结构翘曲，开裂，分层和爆米花效应。 还提供了制造半导体封装的方法。

公开(公告)号：US20050161755A1

公开(公告)日：2005-07-28

申请号：US10763656

申请日：2004-01-23

申请人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

IPC分类号： H01L27/146 ,  H01L31/0203

CPC分类号： H01L31/0203 ,  H01L27/14618 ,  H01L2224/04042 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor package with a photosensitive chip and a fabrication method thereof are provided. A substrate having a core is prepared. A solder mask layer is applied over a surface of the core and formed with an opening to expose a continuous peripheral portion on the surface of the core. At least one photosensitive chip is mounted on and electrically connected to the substrate. An encapsulation dam is formed on the continuous peripheral portion of the core and surrounds the chip. The dam includes a shoulder portion adjacent to and flush with the solder mask layer, and a protruded support portion surrounding the shoulder portion. A lid is attached to the support portion of the dam for sealing the dam such that the chip is received in a space defined by the substrate, the dam and the lid.

摘要翻译： 提供具有感光芯片的半导体封装及其制造方法。 制备具有芯的衬底。 将焊接掩模层施加在芯的表面上并形成有开口以暴露芯的表面上的连续周边部分。 至少一个感光芯片安装在基板上并与其电连接。 在芯的连续外围部分上形成封装坝，并围绕芯片。 大坝包括与焊料掩模层相邻并与其齐平的肩部，以及围绕肩部的突出的支撑部。 盖子附接到坝的支撑部分，用于密封坝，使得芯片被容纳在由基板，坝和盖子限定的空间中。

公开(公告)号：US06306682B1

公开(公告)日：2001-10-23

申请号：US09547157

申请日：2000-04-11

申请人： Chien-Ping Huang ,  Randy H. Y. Lo ,  Tzong-Da Ho ,  Eric Ko ,  Jui-Meng Jao

发明人： Chien-Ping Huang ,  Randy H. Y. Lo ,  Tzong-Da Ho ,  Eric Ko ,  Jui-Meng Jao

IPC分类号： H01L2144

CPC分类号： H01L21/56 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A method of fabricating a BGA (Ball Grid Array) IC package of the type having an encapsulating body is proposed, which allows the BGA IC package to be manufactured without having to use conventional organic substrate and encapsulating-body mold having cavity, so that the manufacture process can be more cost-effective to carry out than the prior art. The proposed method is characterized in the use of a copper piece which is selectively removed to form an encapsulating-body cavity for the forming of an encapsulating body therein. The proposed method requires no use of mold with cavity for the forming of the encapsulating body, allowing the same mold to be used for the fabrication of various BGA IC packages of different sizes. Moreover, the proposed method allows fan-in design as well as fan-out design, thus allowing the number of I/O ports to be increased while making the overall package configuration compact in size, and also allows the implantation of the electrically-conductive balls to be easier to carry out and more precisely controlled than the prior art, making the ball implantation more assured in quality than the prior art. Therefore, the proposed method is more advantageous and cost-effective to use than the prior art.

摘要翻译： 提出了一种制造具有封装体的BGA（球栅阵列）IC封装的方法，其允许制造BGA IC封装，而不必使用传统的有机衬底和具有空腔的封装体模具， 制造工艺比现有技术更具成本效益。 所提出的方法的特征在于使用铜片，其被选择性地去除以形成用于在其中形成封装体的封装体腔体。 所提出的方法不需要使用具有空腔的模具来形成封装体，允许相同的模具用于制造不同尺寸的各种BGA IC封装。 此外，所提出的方法允许风扇设计以及扇出式设计，从而允许增加I / O端口的数量，同时使整个封装结构的尺寸紧凑，并且还允许将导电 球比现有技术更容易实施和更精确地控制，使得球注入在质量上比现有技术更加确保。 因此，所提出的方法比现有技术更有利且成本有效。

公开(公告)号：US06414385B1

公开(公告)日：2002-07-02

申请号：US09475008

申请日：1999-12-30

申请人： Chien-Ping Huang ,  Eric Ko

发明人： Chien-Ping Huang ,  Eric Ko

IPC分类号： H01L2348

CPC分类号： H01L23/3114 ,  H01L23/4334 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A Quad Flat Non-Lead package of semiconductor comprises a chip, a plurality of leads, and a molding compound. The chip has its active surface bonded to the die pad, and the area of the die pad is smaller than that of the chip in order to expose the bonding pad on the active surface of the chip. The leads are disposed at the periphery of the die pad. A plurality of bonding wires is used to electrically connect the top surface of the leads to the bonding pads. The molding compound encapsulates the chip, the die pad, the bonding wires, and a portion of the surface of the leads. In this way, the encapsulating process make the side surface of the lead, and the portion excluding the wire-bonding protruded zone of the bottom surface of the lead exposed in order to make the leads become the external connections of the package structure.

摘要翻译： 半导体的四极扁平非引线封装包括芯片，多个引线和模制化合物。 芯片具有与芯片焊盘接合的活性表面，并且芯片的面积小于芯片的面积，以露出芯片的有效表面上的焊盘。 引线设置在管芯焊盘的周边。 多个接合线用于将引线的顶表面电连接到接合焊盘。 模塑料封装芯片，芯片焊盘，接合线以及引线表面的一部分。 以这种方式，封装工艺使引线的侧表面，并且除了引线的底表面的引线接合突出区域之外的部分暴露以使引线变成封装结构的外部连接。

公开(公告)号：US06198171B1

公开(公告)日：2001-03-06

申请号：US09475003

申请日：1999-12-30

申请人： Chien-Ping Huang ,  Eric Ko

发明人： Chien-Ping Huang ,  Eric Ko

IPC分类号： H01L2348

CPC分类号： H01L23/4951 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/06135 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2224/05599

摘要： A thermally enhanced quad flat non-lead package of semiconductor comprises a chip a plurality of leads, and a molding compound. The chip has its active surface bonded to the top surface of the die pad, and the area of the die pad is smaller than that of the chip in order to expose the bonding pads on the active surface of the chip. The leads are disposed at the periphery of the die pad wherein the bottom surface of the lead has a stepped structure with a relatively thin portion to form a wire-bonding protruded zone. A plurality of bonding wires is used to electrically connect the wire-bonding protruded zone of the leads to the bonding pads of the chip. The molding compound encapsulates the chip, bonding wires, the die pad, and a portion of the surface of the leads, but exposes the bottom surface of the die pad. In this way, the encapsulating process makes the side surface of the lead, and the portion excluding the wire-bonding protruded zone of the bottom surface of the lead exposed in order to make the lead become the external connecting points of the package structure.

摘要翻译： 热增强型四边形半导体封装包括多个引线的芯片和模制化合物。 该芯片具有与芯片焊盘的顶表面结合的活性表面，并且芯片焊盘的面积小于芯片的面积，以露出芯片的有源表面上的焊盘。 引线设置在芯片焊盘的周边处，其中引线的底表面具有相对薄的部分的阶梯状结构，以形成引线接合突出区域。 使用多个接合线将导线的引线接合突出区域电连接到芯片的接合焊盘。 模塑料封装芯片，接合线，芯片焊盘和引线表面的一部分，但是露出芯片焊盘的底表面。 以这种方式，封装工艺使引线的侧表面，并且除了引线的底表面的引线接合突出区域之外的部分暴露以使引线变成封装结构的外部连接点。