公开(公告)号：US06764914B2

公开(公告)日：2004-07-20

申请号：US10290130

申请日：2002-11-07

申请人： Alex See ,  Cher Liang Randall Cha ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

发明人： Alex See ,  Cher Liang Randall Cha ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/31683

摘要： A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.

摘要翻译： 在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数（高K）层，其特征在于底层金属层的局部氧化， 已经开发 该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。 激光烧蚀过程仅在激光点产生所需的高温，允许在该温度下产生高K层，而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度 。 第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序，暴露于UV或I线程序的下面的金属层的区域， 通过覆盖光刻板中的透明区域。 该过程还导致在下面的金属层的顶部上形成高K层。

公开(公告)号：US06734072B1

公开(公告)日：2004-05-11

申请号：US10379814

申请日：2003-03-05

申请人： Yung Fu Chong ,  Alex See

发明人： Yung Fu Chong ,  Alex See

IPC分类号： H01L21336

CPC分类号： H01L21/28211 ,  H01L21/28202 ,  H01L29/1054 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66606

摘要： A method of forming a conductive gate structure on an underlying gate insulator layer, without the use of a plasma dry etch conductive gate definition procedure, has been developed. After formation of source/drain extension (SDE) and heavily doped source/drain regions, an opening is formed in a planarized dielectric layer exposing the top surface of a semiconductor alloy layer, or exposing the top surface of a semiconductor substrate, while the planarized dielectric layer and adjacent insulator spacers overlay the source/drain regions. A multiple spike, rapid thermal oxidation (RTO) procedure is employed to grow a gate insulator layer on the region of semiconductor alloy, or semiconductor, exposed in the opening, with the low temperature RTO procedure, and the planarized dielectric layer overlying the source/drain regions, suppressing out diffusion of SDE dopants. A conductive layer is next deposited and then planarized via a chemical mechanical polishing procedure, resulting in the definition of a conductive gate structure on the gate insulator layer, with the conductive gate structure formed without employment of plasma dry etching eliminating the risk of plasma induced damage of the gate insulator layer.

摘要翻译： 已经开发了在下面的栅极绝缘体层上形成导电栅极结构的方法，而不使用等离子体干蚀刻导电栅极定义程序。 在形成源极/漏极延伸（SDE）和重掺杂源极/漏极区之后，在平坦化介电层中形成开口，暴露半导体合金层的顶表面，或暴露半导体衬底的顶表面，同时平坦化 电介质层和相邻的绝缘体间隔物覆盖源极/漏极区域。 采用多重峰值快速热氧化（RTO）方法，在半导体合金或半导体区域中，在低温RTO工艺下，在开口部分暴露的半导体区域上生长栅极绝缘体层，并且覆盖源极/ 漏区，抑制SDE掺杂物的扩散。 接着沉积导电层，然后通过化学机械抛光程序平坦化，导致栅极绝缘体层上的导电栅极结构的定义，导电栅极结构形成而不需要等离子体干蚀刻，消除了等离子体诱发损伤的风险 的栅极绝缘体层。

公开(公告)号：US06727151B2

公开(公告)日：2004-04-27

申请号：US10213562

申请日：2002-08-07

申请人： Yung Fu Chong ,  Randall Cher Liang Cha ,  Alex See

发明人： Yung Fu Chong ,  Randall Cher Liang Cha ,  Alex See

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66651 ,  H01L29/7834

摘要： A method for forming a MOSFET having an elevated source/drain structure is described. A sacrificial oxide layer is provided on a substrate. A polish stop layer is deposited overlying the sacrificial oxide layer. An oxide layer is deposited overlying the polish stop layer. An opening is formed through the oxide layer and the polish stop layer to the sacrificial oxide layer. First polysilicon spacers are formed on sidewalls of the opening wherein the first polysilicon spacers form an elevated source/drain structure. Second polysilicon spacers are formed on the first polysilicon spacers. The oxide layer and sacrificial oxide layer exposed within the opening are removed. An epitaxial silicon layer is grown within the opening. A gate dielectric layer is formed within the opening overlying the second polysilicon spacers and the epitaxial silicon layer. A gate material layer is deposited within the opening. The gate material layer, first polysilicon spacers and second polysilicon spacers are polished back to the polish stop layer thereby completing formation of a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device.

摘要翻译： 描述了一种形成具有升高的源极/漏极结构的MOSFET的方法。 牺牲氧化物层设置在基板上。 抛光停止层沉积在牺牲氧化物层上。 沉积在抛光停止层上的氧化物层。 通过氧化物层和抛光停止层形成到牺牲氧化物层的开口。 第一多晶硅间隔物形成在开口的侧壁上，其中第一多晶硅间隔物形成升高的源极/漏极结构。 在第一多晶硅间隔物上形成第二多晶硅间隔物。 去除暴露在开口内的氧化物层和牺牲氧化物层。 在开口内生长外延硅层。 在覆盖第二多晶硅间隔物和外延硅层的开口内形成栅介质层。 栅极材料层沉积在开口内。 栅极材料层，第一多晶硅间隔物和第二多晶硅间隔物被抛光回到抛光停止层，从而在集成电路器件的制造中完成形成具有升高的源极/漏极结构的MOSFET。

公开(公告)号：US06638365B2

公开(公告)日：2003-10-28

申请号：US09972504

申请日：2001-10-09

申请人： Jianhui Ye ,  Simon Chooi ,  Alex See

发明人： Jianhui Ye ,  Simon Chooi ,  Alex See

IPC分类号： B08B300

CPC分类号： H01L21/02052 ,  C11D7/08 ,  C11D7/10 ,  C11D11/0047 ,  Y10S134/902

摘要： A method of preparing a silicon surface for a subsequent processing said such as thermal oxidation, or metal silicide formation, via use of a novel wet chemical clean procedure, has been developed. The novel wet chemical clean procedure is comprised of three specific stages, with the first stage featuring the removal of organic contaminants and the growth of a native oxide layer on the silicon surface. A second stage features removal of the native oxide layer and removal of metallic contaminants from the silicon surface, while the third stage is used to dry the silicon surface. The novel wet chemical clean procedure is performed in less time, and using less chemicals, then counterpart wet chemical cleans also used for the preparation of silicon surfaces for subsequent processing steps.

摘要翻译： 已经开发了通过使用新的湿化学清洁程序来制备用于后续处理的硅表面的方法，例如热氧化或金属硅化物形成。 新型湿化学清洁程序由三个特定阶段组成，第一阶段的特征在于去除有机污染物和硅表面上的自然氧化物层的生长。 第二阶段特征在于去除天然氧化物层并从硅表面去除金属污染物，而第三阶段用于干燥硅表面。 新的湿化学清洁程序在较短的时间内进行，使用较少的化学品，然后对应的湿化学清洗也用于制备硅表面用于后续处理步骤。

公开(公告)号：US06630405B1

公开(公告)日：2003-10-07

申请号：US09467136

申请日：1999-12-20

申请人： Lai Weng Hong ,  Alex See

发明人： Lai Weng Hong ,  Alex See

IPC分类号： H01L21302

CPC分类号： H01L21/32137 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/28123

摘要： A method of gate patterning, including the following steps. A semiconductor structure having an upper silicon layer is provided. The semiconductor structure has a gate conductor region. A first gate oxide layer is formed over the semiconductor structure. A polysilicon layer is formed over the first gate oxide layer. A patterned oxide mask and photoresist layer are formed over the polysilicon layer within the gate conductor region leaving unmasked polysilicon layer portions and unmasked first gate oxide layer portions. An oxygen implant is conducted within the unmasked polysilicon layer portions proximate the unmasked first gate oxide layer portions. The patterned photoresist mask is removed. The structure is annealed to form second gate oxide portions within the unmasked polysilicon layer portions over the unmasked first gate oxide layer portions. The unmasked polysilicon layer portions are etched and removed to the second gate oxide portions forming a polysilicon gate conductor within the gate conductor region.

摘要翻译： 一种栅极图案化方法，包括以下步骤。 提供具有上硅层的半导体结构。 半导体结构具有栅极导体区域。 在半导体结构上形成第一栅极氧化物层。 在第一栅极氧化物层上形成多晶硅层。 在栅极导体区域内的多晶硅层上形成图案化的氧化物掩模和光致抗蚀剂层，留下未掩蔽的多晶硅层部分和未屏蔽的第一栅极氧化物层部分。 在未掩蔽的第一栅极氧化物层部分附近的未掩模多晶硅层部分内进行氧注入。 去除图案化的光致抗蚀剂掩模。 将该结构退火以在未屏蔽的第一栅极氧化物层部分上的未屏蔽的多晶硅层部分内形成第二栅极氧化物部分。 未掩模的多晶硅层部分被蚀刻并移除到在栅极导体区域内形成多晶硅栅极导体的第二栅极氧化物部分。

公开(公告)号：US06380084B1

公开(公告)日：2002-04-30

申请号：US09678621

申请日：2000-10-02

申请人： Yeow Kheng Lim ,  Alex See ,  Cher Liang Cha ,  Subhash Gupta ,  Wang Ling Goh ,  Man Siu Tse

发明人： Yeow Kheng Lim ,  Alex See ,  Cher Liang Cha ,  Subhash Gupta ,  Wang Ling Goh ,  Man Siu Tse

IPC分类号： H01L2144

CPC分类号： H01L21/76844 ,  H01L21/32051 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to form robust dual damascene interconnects by decoupling via and connective line trench filling has been achieved. A first dielectric layer is deposited overlying a silicon nitride layer. A shielding layer is deposited. The shielding layer, the first dielectric layer, and the silicon nitride layer are patterned to form via trenches. A first barrier layer is deposited to line the trenches. The via trenches are filled with a first copper layer by a single deposition or by depositing a seed layer and then electroless or electrochemical plating. The first copper layer is polished down to complete the vias. A second barrier layer is deposited. The second barrier layer is patterned to form via caps. A second dielectric layer is deposited. A capping layer is deposited. The capping layer and the second dielectric layer are patterned to form connective line trenches that expose a part of the via caps. A third barrier layer is deposited to line the connective line trenches. The third barrier layer and the via caps are etched to form trench barrier sidewall spacers and to expose the vias. The connective line trenches are filled with a second copper layer by a single deposition, by a first deposition of a seed layer followed by plating, or by plating using the via as the seed layer. The second copper layer is polished down.

摘要翻译： 已经实现了通过解耦通孔和连接线沟槽填充形成鲁棒的双镶嵌互连的方法。 沉积在氮化硅层上的第一介电层。 屏蔽层被沉积。 将屏蔽层，第一介电层和氮化硅层图案化以形成通孔沟槽。 沉积第一势垒层以对沟槽进行排列。 通过单个沉积或通过沉积种子层然后进行无电镀或电化学电镀，将通孔沟槽填充有第一铜层。 第一个铜层被抛光以完成通孔。 沉积第二阻挡层。 图案化第二阻挡层以形成通孔。 沉积第二介电层。 沉积覆盖层。 图案化覆盖层和第二介电层以形成连接线沟槽，其暴露通孔盖的一部分。 沉积第三阻挡层以对连接线沟槽进行排列。 蚀刻第三阻挡层和通孔盖以形成沟槽阻挡侧壁间隔件并露出通孔。 连接线沟槽通过单次沉积，通过第一次沉积种子层，然后电镀，或通过使用通孔作为种子层进行电镀，填充第二铜层。 第二个铜层被抛光。

公开(公告)号：US06365446B1

公开(公告)日：2002-04-02

申请号：US09609751

申请日：2000-07-03

申请人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

发明人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

IPC分类号： H01L21336

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/268 ,  H01L21/28052 ,  H01L29/665

摘要： A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method that involves pre-amorphization of the gate, source and drain regions by ion-implantation, the formation of a metal layer, ion implantation through the metal layer, the formation of a capping layer and a subsequent laser anneal.

摘要翻译： 一种用于制造具有深源极/漏极结的MOS型晶体管和具有期望的界面和电学性质的薄的硅化物触点的方法。 这些器件通过一种方法产生，该方法涉及通过离子注入，栅极，源极和漏极区域的非晶化，金属层的形成，通过金属层的离子注入，形成覆盖层和随后的激光退火 。

公开(公告)号：US06355563B1

公开(公告)日：2002-03-12

申请号：US09798652

申请日：2001-03-05

申请人： Randall Cher Liang Cha ,  Alex See ,  Yeow Kheng Lim ,  Tae Jong Lee ,  Lap Chan

发明人： Randall Cher Liang Cha ,  Alex See ,  Yeow Kheng Lim ,  Tae Jong Lee ,  Lap Chan

IPC分类号： H01L2144

CPC分类号： H01L21/76802 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76832

摘要： A method to integrate low dielectric constant dielectric materials with copper metallization is described. A metal line is provided overlying a semiconductor substrate and having a nitride capping layer thereover. A polysilicon layer is deposited over the nitride layer and patterned to form dummy vias. A dielectric liner layer is conformally deposited overlying the nitride layer and dummy vias. A dielectric layer having a low dielectric constant is spun-on overlying the liner layer and covering the dummy vias. The dielectric layer is polished down whereby the dummy vias are exposed. Thereafter, the dielectric layer is cured whereby a cross-linked surface layer is formed. The dummy vias are removed thereby exposing a portion of the nitride layer within the via openings. The exposed nitride layer is removed. The via openings are filled with a copper layer which is planarized to complete copper metallization in the fabrication of an integrated circuit device.

摘要翻译： 描述了一种将低介电常数电介质材料与铜金属化相结合的方法。 金属线设置在半导体衬底上并且在其上具有氮化物覆盖层。 多晶硅层沉积在氮化物层上并被图案化以形成虚拟通孔。 电介质衬垫层共形沉积在氮化物层和虚拟通孔之上。 将具有低介电常数的介电层旋涂在衬层上并覆盖虚拟通孔。 抛光电介质层，从而暴露虚拟通孔。 此后，电介质层被固化，由此形成交联表面层。 去除虚设通孔，从而将通孔的一部分氮化物层露出。 去除暴露的氮化物层。 通孔开口填充有铜层，该铜层在集成电路器件的制造中被平坦化以完成铜金属化。

公开(公告)号：US06348385B1

公开(公告)日：2002-02-19

申请号：US09726256

申请日：2000-11-30

申请人： Randall Cher Liang Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Chee Tee Chua

发明人： Randall Cher Liang Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Chee Tee Chua

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  H01L21/2255 ,  H01L21/28167 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/7834

摘要： The method for a transistor using a replacement gate process that has a doped low-K dielectric spacer that lowers the junction capacitance. A dummy gate is formed over a substrate. Ions are implanted into the substrate using the dummy gate as an implant mask to form source and drain regions. A masking layer is formed on the substrate over the source and drain regions. We remove the dummy gate. Doped low k spacers are formed on the sidewalls of the masking layer. The doped spacers are heated to diffuse dopant into the substrate to form lightly doped drain (LDD regions). We form a high k gate dielectric layer over the masking layer. A gate layer is formed over the high K dielectric layer. The gate layer is chemical-mechanical polished (CMP) to form a gate over the high k dielectric layer and to remove the gate layer over the masking layer.

摘要翻译： 使用具有降低结电容的掺杂低K电介质间隔物的替代栅极工艺的晶体管的方法。 在基板上形成虚拟栅极。 使用伪栅极作为注入掩模将离子注入到衬底中以形成源区和漏区。 在源极和漏极区上的衬底上形成掩模层。 我们删除虚拟门。 在掩蔽层的侧壁上形成掺杂的低k间隔物。 掺杂的间隔物被加热以将掺杂剂扩散到衬底中以形成轻掺杂漏极（LDD区）。 我们在掩模层上形成一个高k栅介质层。 在高K电介质层上形成栅极层。 栅极层是化学机械抛光（CMP），以在高k电介质层上形成栅极，并且去除掩模层上的栅极层。

公开(公告)号：US06335253B1

公开(公告)日：2002-01-01

申请号：US09614557

申请日：2000-07-12

申请人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See ,  Andrew Thye Shen Wee

发明人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See ,  Andrew Thye Shen Wee

IPC分类号： H01L21336

CPC分类号： H01L21/268 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/665 ,  H01L29/6659

摘要： A new method of forming MOS transistors with shallow source and drain extensions and self-aligned silicide in the has been achieved. Gates are provided overlying a semiconductor substrate. Temporary sidewall spacers are formed on the gates. Ions are implanted into the semiconductor substrate and the polysilicon layer to form deep amorphous layers beside the spacers and shallow amorphous layers under the spacers. The spacers are removed. Ions are implanted to form lightly doped junctions in the shallower amorphous layer. Permanent sidewall spacers are formed on the gates. Ions are implanted to form heavily doped junctions in the deeper amorphous layer. A metal layer is deposited. A capping layer is deposited to protect the metal layer during irradiation. The integrated circuit device is irradiated with laser light to melt the amorphous layer while the crystalline polysilicon and semiconductor substrate remain in solid state. The metal layer is heated, and may be melted, to cause reaction with the silicon to form silicide. Ions in the heavily doped junctions and in the lightly doped junctions are also thereby diffused into the amorphous layer. The deep source and drain junctions, the shallow source and drain extensions, and a silicide layer are simultaneously formed. A heat treatment crystallizes the silicide to improve resistivity.

摘要翻译： 已经实现了一种形成具有浅源极和漏极延伸和自对准硅化物的MOS晶体管的新方法。 盖板覆盖半导体衬底。 在门上形成临时侧墙。 将离子注入到半导体衬底和多晶硅层中，以在间隔物旁边的隔离层和浅非晶层之间形成深非晶层。 去除间隔物。 在较浅的非晶层中植入离子以形成轻掺杂的结。 在门上形成永久侧壁间隔物。 植入离子以在较深的非晶层中形成重掺杂的结。 沉积金属层。 沉积覆盖层以在照射期间保护金属层。 用激光照射集成电路器件以熔化非晶层，同时晶体多晶硅和半导体衬底保持固态。 金属层被加热并且可能被熔化，从而与硅反应形成硅化物。 在重掺杂结和轻掺杂结中的离子也因此扩散到非晶层中。 同时形成深源极和漏极结，浅源极和漏极延伸部分以及硅化物层。 热处理使硅化物结晶以提高电阻率。