公开(公告)号：US5912840A

公开(公告)日：1999-06-15

申请号：US916117

申请日：1997-08-21

申请人： Fernando Gonzalez ,  David Kao

发明人： Fernando Gonzalez ,  David Kao

IPC分类号： G11C11/404 ,  G11C16/04

CPC分类号： G11C11/404 ,  G11C16/0433

摘要： A memory cell architecture utilizing a dual access gate and dual wordlines is disclosed. The cell is comprised of a first transistor connected between a digitline and a cellplate. The transistor is responsive to a read wordline to enable the cell to be read. An active device, such as a second transistor, is provided for modifying at least one conductive characteristic of the first transistor according to the state of a signal on the digitline. The conductive characteristic that is modified may be, for example, the threshold voltage or the transistor's channel resistance. Modification of the first transistor's characteristics is representative of writing information to the memory cell. A circuit structure for implementing the circuit architecture is also disclosed together with a method of operating a memory cell.

摘要翻译： 公开了一种利用双存取门和双字线的存储单元架构。 该单元由连接在数字线和单元板之间的第一晶体管组成。 晶体管响应读取字线以使得单元被读取。 提供诸如第二晶体管的有源器件，用于根据数字线上的信号的状态修改第一晶体管的至少一个导电特性。 修改的导电特性可以是例如阈值电压或晶体管的沟道电阻。 第一晶体管特性的修改代表向存储单元写入信息。 还公开了一种用于实现电路架构的电路结构以及操作存储器单元的方法。

公开(公告)号：US5897363A

公开(公告)日：1999-04-27

申请号：US982809

申请日：1997-12-02

申请人： Fernando Gonzalez ,  Randhir Thakur

发明人： Fernando Gonzalez ,  Randhir Thakur

IPC分类号： H01L21/223 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/6659 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/7833 ,  H01L29/7836 ,  H01L29/66575 ,  Y10S257/90

摘要： Disclosed is a process for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention comprises, first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. An anneal step follows. The result is a shallow junction with a variable concentration profile gradation of dopant. The junction is suitable for forming source and drain regions in MOS transistors, especially where a contact or interconnect is intended to engage the source and drain regions. The variable concentration profile gradation of dopants helps to maintain proper threshold voltage levels and reduces reverse bias current leakage.

摘要翻译： 公开了一种用于形成具有可变浓度分布层级的掺杂剂的浅结的方法。 本发明的方法包括：首先提供和掩蔽要在其上形成浅结的过程中集成电路晶片上的表面。 接下来，进行低离子速度和低能离子轰击等离子体掺杂或PLAD操作以提供浅结的高掺杂内部部分。 在另一步骤中，使用中功率注入机进行较高的离子速度和能量常规的离子轰击注入掺杂操作，以用轻掺杂的外部部分延伸浅结边界。 退火步骤如下。 结果是具有掺杂剂的可变浓度分布灰度的浅结。 该结适用于在MOS晶体管中形成源极和漏极区域，特别是在接触或互连用于接合源极和漏极区域的情况下。 掺杂剂的可变浓度分布层次有助于保持适当的阈值电压电平并减少反向偏置电流泄漏。

公开(公告)号：US5714786A

公开(公告)日：1998-02-03

申请号：US741828

申请日：1996-10-31

申请人： Fernando Gonzalez ,  David Kao

发明人： Fernando Gonzalez ,  David Kao

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/108 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66484 ,  H01L21/28132 ,  H01L21/823468 ,  H01L27/088 ,  H01L27/108 ,  H01L29/4983 ,  H01L29/7831 ,  H01L21/28114

摘要： An improved transistor structure includes an insulated conductive gate spacer which is contacted and driven separately from the gate of the transistor. The gate spacer serves as a control or second gate for the transistor and may be used throughout an integrated circuit or it may be preferred to use the improved transistor only in critical speed paths of an integrated circuit. Delays within circuits including the improved transistor are reduced since the drain voltage can be higher than VCC and the BVDSS and subthreshold voltage are substantially higher than standard LDD transistors. When the improved transistor is used selectively within an integrated circuit, the remaining devices can be structured as standard LDD transistors using the gate spacers in a conventional manner.

摘要翻译： 改进的晶体管结构包括与晶体管的栅极分开接触并驱动的绝缘导电栅极间隔物。 栅极间隔物用作晶体管的控制或第二栅极，并且可以在整个集成电路中使用，或者可以优选仅在集成电路的临界速度路径中使用改进的晶体管。 包括改进的晶体管在内的电路中的延迟减小，因为漏极电压可以高于VCC，并且BVDSS和亚阈值电压显着高于标准LDD晶体管。 当改进的晶体管被​​选择性地用于集成电路内时，其余器件可以以常规方式使用栅极间隔来构造为标准LDD晶体管。

公开(公告)号：US5654227A

公开(公告)日：1997-08-05

申请号：US590313

申请日：1996-01-23

申请人： Fernando Gonzalez ,  Mike Violette

发明人： Fernando Gonzalez ,  Mike Violette

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76202 ,  H01L21/32

摘要： A method for forming field oxide comprises the steps of forming a pad oxide layer over a semiconductor substrate, then forming a silicon layer over the pad oxide layer. A patterned mask is formed over the silicon layer and the silicon layer is etched to form openings in the silicon layer. Next, a blanket nitride layer is formed over the silicon and within the openings, and the nitride layer is then planarized to remove the nitride which overlies the silicon which leaves the nitride in the openings. Subsequent to the step of planarizing the nitride, the silicon layer is removed thereby forming openings in the nitride layer. The substrate is oxidized at the openings in the nitride layer to form field oxide from the substrate.

摘要翻译： 形成场氧化物的方法包括以下步骤：在半导体衬底上形成衬垫氧化层，然后在衬垫氧化物层上形成硅层。 在硅层上形成图案化掩模，并且蚀刻硅层以在硅层中形成开口。 接下来，在硅上和开口内形成覆盖氮化物层，然后使氮化物层平坦化，以去除在开口中离开氮化物的硅上的氮化物。 在氮化物平坦化步骤之后，去除硅层，从而在氮化物层中形成开口。 衬底在氮化物层的开口处被氧化以从衬底形成场氧化物。

公开(公告)号：US5646075A

公开(公告)日：1997-07-08

申请号：US559511

申请日：1995-11-15

申请人： Randhir P. S. Thakur ,  Fernando Gonzalez

发明人： Randhir P. S. Thakur ,  Fernando Gonzalez

IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L21/324 ,  H01L21/477

CPC分类号： H01L21/31058 ,  H01L21/316 ,  H01L21/76819 ,  Y10S148/133

摘要： The present invention teaches a method for fabricating semiconductors. The method initially comprises the step of forming a conformal layer superjacent at least two conductive layers. The conformal layer preferably comprises tetraethylorthosilicate ("TEOS") and has a thickness of at least 50 .ANG.. Subsequently, a barrier layer is formed superjacent the conformal layer to prevent subsequent layers from diffusing into active regions. The barrier layer preferably comprises Si.sub.3 N.sub.4, though other suitable materials known to one of ordinary skill in the art may be employed. Further, a glass layer is then formed superjacent the barrier layer. The glass layer comprises at least one of SiO.sub.2, phosphosilicate glass, borosilicate glass, and borophosphosilicate glass, and has a thickness of at least 1 k.ANG.. Upon forming the glass layer, the glass layer is heated to a temperature of at least 800.degree. C. for at least 15 minutes while introducing H.sub.2 and O.sub.2 at a substantially high temperature to cause vaporization, thereby causing the glass layer to reflow. Next, the glass layer is exposed to a gas and radiant energy for approximately 5 seconds to 60 seconds, thereby making said glass layer substantially planar. The radiant energy generates a temperature substantially within the range of 700.degree. C. to 1250.degree. C. Further, the gas comprises at least one of N.sub.2, NH.sub.3, O.sub.2, N.sub.2 O, Ar, Ar--H.sub.2, H.sub.2, GeH.sub.4, and a Fluorine based gas.

摘要翻译： 本发明教导了半导体制造方法。 该方法最初包括在至少两个导电层之上形成保形层的步骤。 共形层优选包括原硅酸四乙酯（“TEOS”），并且具有至少50的厚度。 随后，在保形层之上形成阻挡层，以防止随后的层扩散到活性区域。 阻挡层优选包含Si 3 N 4，尽管可以使用本领域普通技术人员已知的其它合适的材料。 此外，然后在阻挡层的上方形成玻璃层。 玻璃层包括SiO 2，磷硅酸盐玻璃，硼硅酸盐玻璃和硼磷硅酸盐玻璃中的至少一种，并且具有至少1k ANGSTROM的厚度。 在形成玻璃层时，将玻璃层加热到至少800℃的温度至少15分钟，同时在基本上高的温度下引入H 2和O 2以引起气化，从而使玻璃层回流。 接下来，玻璃层暴露于气体和辐射能量约5秒至60秒，从而使所述玻璃层基本上是平面的。 辐射能产生基本上在700℃至1250℃范围内的温度。此外，气体包括N 2，NH 3，O 2，N 2 O，Ar，Ar-H 2，H 2，GeH 4和氟中的至少一种 基气体。

公开(公告)号：US5608249A

公开(公告)日：1997-03-04

申请号：US558442

申请日：1995-11-16

申请人： Fernando Gonzalez

发明人： Fernando Gonzalez

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10852

摘要： An improved storage node junction between a doped active area in a semiconductor substrate and an overlying layer of polysilicon, such as the storage node junction in a DRAM memory cell. The area and perimeter of the storage node junction is significantly reduced and the junction is moved away from the adjacent isolation structure. An exemplary semiconductor device incorporating the new junction includes a storage node junction between a conductive polysilicon layer and an active area on a semiconductor substrate, the substrate having been subjected to LOCOS steps to create active areas bounded by a region of field oxide. An insulated gate electrode is formed over an active area on the substrate, which has been doped to a first conductivity type. A contact region comprising a portion of the active area extends laterally between one side of the gate electrode and the field oxide region. The contact region has a first segment adjacent to the gate electrode and a second segment interposed between the first segment and the field oxide region. The first segment is thereby isolated from the field oxide region by the second segment. The first segment is doped to a second conductivity type. A layer of storage polysilicon is formed in electrical contact with the first segment of the contact region but not the second segment of the contact region. The storage polysilicon is isolated from the field oxide through an insulating layer interposed between the storage polysilicon and the second segment of the contact region.

摘要翻译： 半导体衬底中的掺杂有源区和多晶硅上层之间的改进的存储节点结，诸如DRAM存储单元中的存储节点结。 存储节点结的面积和周长显着减小，并且结点从相邻隔离结构移开。 结合新结的示例性半导体器件包括在导电多晶硅层和半导体衬底上的有源区之间的存储节点结，衬底已经经过LOCOS步骤以产生由场氧化物区域界定的有源区。 在衬底上的有源区域上形成绝缘栅电极，其已被掺杂到第一导电类型。 包括有源区域的一部分的接触区域在栅电极的一侧和场氧化物区域之间横向延伸。 接触区域具有与栅电极相邻的第一段和介于第一段和场氧化物区之间的第二段。 因此，第一段由第二段与场氧化物区隔离。 第一段被掺杂到第二导电类型。 形成与接触区域的第一段电接触而不是接触区域的第二段的存储多晶硅层。 存储多晶硅通过介于存储多晶硅和接触区域的第二段之间的绝缘层与场氧化物隔离。

公开(公告)号：US5572461A

公开(公告)日：1996-11-05

申请号：US388873

申请日：1995-02-14

申请人： Fernando Gonzalez

发明人： Fernando Gonzalez

IPC分类号： G11C11/402 ,  H01L27/11 ,  G11C11/00

CPC分类号： H01L27/11 ,  G11C11/402 ,  G11C11/4023 ,  Y10S257/903

摘要： The present invention is a three-transistor (3-T) SRAM cell that is made up of a half latch in combination with a dynamic random access memory (DRAM) cell. In a DRAM cell, the "0" bit state is represented by a discharged cell capacitor--a stable state. The "1" bit state, on the other hand, is represented by a charged cell capacitor--an unstable state, since the capacitor leaks rapidly toward the discharged "0" bit state. The new 3-T SRAM cell incorporates a latch which maintains the charge on the cell capacitor when the cell is in a "1" bit state. The cell circuitry includes a cell access transistor coupled to a capacitor, a pull-down transistor, and a P-channel thin film transistor (TFT) which acts as the capacitor pull-up device, the gate of the P-channel TFT also being the drain of the pull-down transistor. A separate polycrystalline silicon layer functions as the substrate of the TFT pull-up device. The 3-T SRAM cell is one half the size of a 4-T SRAM cell and about twice the size of a DRAM cell.

摘要翻译： 本发明是与动态随机存取存储器（DRAM）单元结合的半锁存器构成的三晶体管（3-T）SRAM单元。 在DRAM单元中，“0”位状态由放电单元电容器表示 - 稳定状态。 另一方面，“1”位状态由充电单元电容器 - 不稳定状态表示，因为电容器迅速向放电的“0”位状态泄漏。 新的3-T SRAM单元包含一个锁存器，当单元处于“1”位状态时，该锁存器保持单元电容器上的电荷。 单元电路包括耦合到电容器的单元存取晶体管，下拉晶体管和用作电容器上拉器件的P沟道薄膜晶体管（TFT），P沟道TFT的栅极也是 下拉晶体管的漏极。 单独的多晶硅层用作TFT上拉器件的衬底。 3-T SRAM单元是4-T SRAM单元的大小的一半，是DRAM单元大小的两倍。

公开(公告)号：US5513137A

公开(公告)日：1996-04-30

申请号：US393584

申请日：1995-02-23

申请人： Roger R. Lee ,  Fernando Gonzalez

发明人： Roger R. Lee ,  Fernando Gonzalez

IPC分类号： G11C29/00 ,  G11C11/34

CPC分类号： G11C29/82

摘要： A flash programmable memory device comprises first and second row lines each having memory elements therealong with the second conductive line functionally replacing the first conductive line. The memory device further includes a first program circuit for programming the memory elements along the first row line, and a second program circuit for programming memory elements along the second row line. A read circuit bypasses the first conductive line during all read cycles and reads the memory elements along the second row line.

摘要翻译： 闪存可编程存储器件包括第一和第二行线，每条线具有存储元件，第二导线在功能上替代第一导线。 存储装置还包括用于沿着第一行线对存储元件进行编程的第一编程电路和用于沿着第二行线对存储元件进行编程的第二编程电路。 读取电路在所有读取周期期间绕过第一导线，并沿着第二行线读取存储器元件。

公开(公告)号：US5453396A

公开(公告)日：1995-09-26

申请号：US250897

申请日：1994-05-31

申请人： Fernando Gonzalez ,  Angus C. Fox, III

发明人： Fernando Gonzalez ,  Angus C. Fox, III

IPC分类号： H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/76 ,  H01L21/336

CPC分类号： H01L27/10844 ,  H01L21/76294 ,  H01L27/10808

摘要： The present invention is a process for forming diffusion areas and field isolation regions on a silicon substrate, by the steps of: growing a field oxide layer on the surface of the substrate; forming a mask pattern which exposes a plurality of spaced-apart regions on the surface of the field oxide layer; removing portions of the field oxide layer in the exposed, spaced-apart regions with an anisotropic etch so as to leave a cavity in each spaced-apart region, each cavity having as its floor an exposed region of the silicon substrate, and having vertical walls of field oxide; angularly chamfering the rim of each cavity with a facet etch; and filling each cavity with silicon using selective epitaxial growth, and using the floor of each cavity as the seed crystal for such growth.

摘要翻译： 本发明是通过以下步骤在硅衬底上形成扩散区域和场隔离区域的方法：在衬底的表面上生长场氧化物层; 形成在场氧化物层的表面上露出多个间隔开的区域的掩模图案; 通过各向异性蚀刻去除暴露的间隔开的区域中的场氧化物层的部分，以便在每个间隔开的区域中留下空腔，每个空腔具有作为其底板的硅衬底的暴露区域，并具有垂直壁 的氧化物; 用小面蚀刻对每个腔的边缘进行角度倒角; 并使用选择性外延生长用硅填充每个腔，并且使用每个腔的底部作为用于这种生长的晶种。

公开(公告)号：US5425392A

公开(公告)日：1995-06-20

申请号：US67660

申请日：1993-05-26

申请人： Randhir P. S. Thakur ,  Fernando Gonzalez ,  Annette L. Martin

发明人： Randhir P. S. Thakur ,  Fernando Gonzalez ,  Annette L. Martin

IPC分类号： H01L21/28 ,  H01L21/8239

CPC分类号： H01L21/28247 ,  H01L21/28061

摘要： The present invention teaches a method for reducing sheet resistance in the fabrication of semiconductor wafers. A silicon substrate having a gate oxide layer thereon is provided in a chamber. Subsequently, a polysilicon layer is formed superjacent the gate oxide layer in situ by exposing the silicon substrate to a first gas comprising at least one of silane, disilane, and dichlorosilane, and radiant energy at a temperature substantially within the range of 500.degree. C. to 1250.degree. C. for at least 10 seconds. The polysilicon substrate can be doped with a material such as phosphorus, arsenic and boron for example, by exposing the polysilicon to a second gas under the stated conditions. A conductive layer comprising at least one of tungsten silicide (WSi.sub.x) and titanium silicide (TiSi.sub.x) can be formed superjacent the polysilicon by exposing the polysilicon to a third gas comprising at least one of WF.sub.6, TMAT and TiCl.sub.4.

摘要翻译： 本发明教导了一种在半导体晶片的制造中降低薄层电阻的方法。 在其中设置有其上具有栅极氧化物层的硅衬底。 随后，通过将硅衬底暴露于包括硅烷，乙硅烷和二氯硅烷中的至少一种的第一气体和基本上在500℃的温度范围内的辐射能，在栅极氧化物层的上方形成多晶硅层。 至1250℃至少10秒钟。 多晶硅衬底可以掺杂例如磷，砷和硼的材料，例如通过在所述条件下将多晶硅暴露于第二气体。 通过将多晶硅暴露于包含WF6，TMAT和TiCl4中的至少一种的第三气体，可以在多晶硅之上形成包括硅化钨（WSix）和硅化钛（TiSix）中的至少一种的导电层。