公开(公告)号：US20190333993A1

公开(公告)日：2019-10-31

申请号：US15961912

申请日：2018-04-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Ruilong Xie ,  Hui Zang ,  Haiting Wang

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  C30B25/04 ,  C30B29/40

Abstract: Methods form an integrated circuit structure that includes complementary transistors on a first layer. An isolation structure is between the complementary transistors. Each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, and insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors. With these methods and structures, an etch stop layer is formed only on the source/drain regions.

公开(公告)号：US10446395B1

公开(公告)日：2019-10-15

申请号：US15950364

申请日：2018-04-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xiaohan Wang ,  Qiang Fang ,  Zhiguo Sun ,  Jinping Liu ,  Hui Zang

IPC: H01L21/033 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning. A mandrel line is patterned from a first mandrel layer disposed on a hardmask and a second mandrel layer disposed over the first mandrel layer. A first section of the second mandrel layer of the mandrel line is removed to expose a first section of the first mandrel layer. The first section of the first mandrel layer is masked, and the second sections of the second mandrel layer and the underlying second portions of the first mandrel layer are removed to expose first portions of the hardmask. The first portions of the hardmask are then removed with an etching process to form a trench in the hardmask. A second portion of the hardmask is masked by the first portion of the first mandrel layer during the etching process to form a cut in the trench.

公开(公告)号：US10431500B1

公开(公告)日：2019-10-01

申请号：US15936734

申请日：2018-03-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Asli Sirman ,  Jiehui Shu ,  Chih-Chiang Chang ,  Huy Cao ,  Haigou Huang ,  Jinping Liu

IPC: H01L21/00 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78

Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.

公开(公告)号：US10418272B1

公开(公告)日：2019-09-17

申请号：US15976326

申请日：2018-05-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Garo Jacques Derderian ,  Hui Zang ,  John Zhang ,  Haigou Huang ,  Jinping Liu

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

Abstract: At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.

公开(公告)号：US20190131429A1

公开(公告)日：2019-05-02

申请号：US15797837

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Chang Seo Park ,  Shimpei Yamaguchi ,  Tao Han ,  Yong Mo Yang ,  Jinping Liu ,  Hyuck Soo Yang

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material, performing a first gate-cut etching process to thereby form an opening in the sacrificial gate electrode material and forming an internal sidewall spacer in the opening. In this example, the method also includes, after forming the internal sidewall spacer, performing a second gate-cut etching process through the opening, the second gate-cut etching process being adapted to remove the sacrificial gate electrode material, performing an oxidizing anneal process and forming an insulating material in at least the opening.

公开(公告)号：US10236213B1

公开(公告)日：2019-03-19

申请号：US15917940

申请日：2018-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shesh M. Pandey ,  Jiehui Shu ,  Hui Zang ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311

Abstract: A gate cut structure for finFETs, and a related method, are disclosed. The gate cut structure separates and electrically isolates an end of a first metal gate conductor of a first finFET from an end of a second metal gate conductor of a second finFET. The gate cut structure includes a body contacting the end of the first and second metal gate conductors. A liner spacer separates a lower portion of the body from an interlayer dielectric (ILD), and an upper portion of the body contacts the ILD. During formation, the liner spacer allows for a larger gate cut opening to be used to allow quality cleaning of the gate cut opening, but also reduction in size of the spacing between metal gate conductor ends of the finFETs. In one example, the body may have a lower portion having a width less than an upper portion thereof.

公开(公告)号：US10229999B2

公开(公告)日：2019-03-12

申请号：US15445392

申请日：2017-02-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Jiehui Shu

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78

Abstract: A plurality of vertically oriented channel semiconductor structures is formed above a substrate. A bottom source/drain (S/D) region is formed proximate a lower portion of the vertically oriented channel semiconductor structure. A first dielectric layer is formed above the vertically oriented channel semiconductor structure. A thickness of the first dielectric layer is reduced to expose an upper portion of the vertically oriented channel semiconductor structure. A first semiconductor material region is formed on the exposed upper portion. The thickness of the first dielectric layer is further reduced to expose a channel portion of the vertically oriented channel semiconductor structure and to define a bottom spacer adjacent the bottom S/D region. A gate structure is formed around the channel region of the vertically oriented channel semiconductor structure. A second semiconductor material region is formed on the upper portion to define an upper S/D region after forming the gate structure.

公开(公告)号：US09966272B1

公开(公告)日：2018-05-08

申请号：US15632931

申请日：2017-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haifeng Sheng ,  Haigou Huang ,  Tai Fong Chao ,  Jiehui Shu ,  Jinping Liu ,  Xingzhao Shi ,  Laertis Economikos

IPC: H01L21/00 ,  H01L21/3105

CPC classification number: H01L21/31056 ,  H01L21/31055 ,  H01L21/762 ,  H01L21/823878

Abstract: The disclosure is directed to methods of planarizing an integrated circuit structure including: forming a dielectric over a first nitride layer; planarizing the dielectric to a top surface of a set of nitride fins in a first region and removing the dielectric from a second region to expose the substantially planar upper surface in a second region; forming a second nitride layer over the dielectric and the top surface of the set of nitride fins and over the substantially planar upper surface; planarizing the second nitride layer such that the second nitride layer in the second region is planar with the top surface of the dielectric and the set of nitride fins, and such that the second nitride layer is removed from the first region; and performing an etch such that the first nitride layer in the first region is planar with the first nitride layer in the second region.

公开(公告)号：US20180108732A1

公开(公告)日：2018-04-19

申请号：US15292808

申请日：2016-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Baofu Zhu ,  Haifeng Sheng ,  Jinping Liu ,  Shesh Mani Pandey ,  Jagar Singh

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/0661 ,  H01L21/3083 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/7851

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to notched fin structures and methods of manufacture. The structure includes: a fin structure composed of a substrate material and a stack of multiple epitaxially grown materials on the substrate material; a notch formed in a first epitaxially grown material of the stack of multiple epitaxially grown materials of the fin structure; an insulator material within the notch of the fin structure; and an insulator layer surrounding the fin structure and above a surface of the notch.

公开(公告)号：US09741610B2

公开(公告)日：2017-08-22

申请号：US14740035

申请日：2015-06-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qiang Fang ,  Zhiguo Sun ,  Jiehui Shu

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L21/311

CPC classification number: H01L21/76879 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/53238

Abstract: A starting metallization structure for electrically coupling one or more underlying semiconductor devices, the structure including a bottom layer of dielectric material with metal-filled via(s) situated therein, a protective layer over the bottom layer, and a top layer of dielectric material over the protective layer. A sacrificial layer of amorphous silicon is formed over the top layer of dielectric material, a protective layer is formed over the sacrificial layer and via(s) through each layer above the metal-filled via(s) to expose the metal of the metal-filled via(s). The protective layer is then selectively removed, as well as the sacrificial layer of amorphous silicon.