公开(公告)号：US20190056671A1

公开(公告)日：2019-02-21

申请号：US15681007

申请日：2017-08-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  John Zhang ,  Shao Beng Law ,  Guoxiang Ning ,  Xunyuan Zhang ,  Ruilong Xie

IPC: G03F7/20 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/544 ,  C23C14/22 ,  C23C16/455

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to overlay mark structures and methods of manufacture. The method includes: forming an overlay mark within a layer of a stack of layers; increasing a density of an upper layer of the stack of layers, above the layer, the increased density protecting the overlay mark; and polishing the upper layer or one or more layers above the upper layer of the stack of layers.

公开(公告)号：US20180342454A1

公开(公告)日：2018-11-29

申请号：US15602801

申请日：2017-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Dongfei Pei ,  Frank W. Mont

IPC: H01L23/528 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/288 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/0332 ,  H01L21/288 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53242

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a plurality of openings in a hardmask material; blocking at least one of the plurality of openings of the hardmask material with a blocking material; etching a skip via to a metallization feature in a stack of metallization features through another of the plurality of openings which is not blocked by the blocking material; and at least partially filling the skip via by a bottom up fill process.

公开(公告)号：US10056291B2

公开(公告)日：2018-08-21

申请号：US15360255

申请日：2016-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shao Beng Law ,  Xunyuan Zhang ,  Frank W. Mont ,  Genevieve Beique ,  Lei Sun

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/285

CPC classification number: H01L21/76816

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to post spacer self-aligned cut structures and methods of manufacture. The method includes: providing a non-mandrel cut; providing a mandrel cut; forming blocking material on underlying conductive material in the non-mandrel cut and the mandrel cut; forming trenches with the blocking material acting as a blocking mask at the mandrel cut and the non-mandrel cut; and filling the trenches with metallization features such that the metallization features have a tip to tip alignment.

公开(公告)号：US10014297B1

公开(公告)日：2018-07-03

申请号：US15589312

申请日：2017-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  Wenhui Wang ,  Xunyuan Zhang ,  Ruilong Xie ,  Jia Zeng ,  Xuelian Zhu ,  Min Gyu Sung ,  Shao Beng Law

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/027 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/823431 ,  H01L29/6681

Abstract: One aspect of the disclosure is directed to a method of forming an integrated circuit structure. The method may include: providing a set of fins over a semiconductor substrate, the set of fins including a plurality of working fins and a plurality of dummy fins, the plurality of dummy fins including a first subset of dummy fins within a pre-defined distance from any of the plurality of working fins, and a second subset of dummy fins beyond the pre-defined distance from any of the plurality of working fins; removing the first subset of dummy fins by an extreme ultraviolet (EUV) lithography technique; and removing at least a portion of the second subset of dummy fins.

公开(公告)号：US09984919B1

公开(公告)日：2018-05-29

申请号：US15664584

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Chanro Park ,  Yongan Xu ,  Peng Xu ,  Yann Mignot

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76807 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53295

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first section of a mandrel is covered with a feature of an etch mask. A top surface of a second section of the mandrel is exposed by the feature of the etch mask and is recessed with an etching process. A conductive via is formed that reproduces a shape of the first section of the mandrel, and a conductive line is formed that reproduces a shape of the second section of the mandrel. The mandrel is removed to release the conductive via and the conductive line.

公开(公告)号：US09837268B2

公开(公告)日：2017-12-05

申请号：US15154444

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Xunyuan Zhang ,  Catherine B. Labelle

IPC: H01L21/02 ,  H01L29/06 ,  H01L21/311 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/02532 ,  H01L21/02639 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench.

公开(公告)号：US09799559B1

公开(公告)日：2017-10-24

申请号：US15158827

申请日：2016-05-19

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Shariq Siddiqui ,  Frank W. Mont ,  Xunyuan Zhang ,  Brown Peethala ,  Douglas M. Trickett

IPC: H01L21/768 ,  H01L21/44 ,  H01L21/311 ,  H01L21/302 ,  H01L21/475 ,  H01L21/469 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/7688 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266

Abstract: A method includes, for example, providing an intermediate semiconductor structure comprising a metallic layer, a patternable layer disposed over the metallic layer, and a hard mask disposed over the patternable layer, the intermediate semiconductor structure comprising a plurality of vias extending through the hard mask onto the metallic layer, depositing a sacrificial barrier layer over the intermediate semiconductor structure and in the plurality of vias, removing a portion of the sacrificial barrier layer between the plurality of vias while maintaining a portion of the sacrificial barrier layer in the plurality of vias, forming a trench in the patternable layer between the removed portion of the sacrificial barrier layer and the plurality of vias, and removing the remaining portions of the sacrificial barrier layer from the plurality of vias.

公开(公告)号：US09721889B1

公开(公告)日：2017-08-01

申请号：US15219378

申请日：2016-07-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chengyu C. Niu ,  Vimal K. Kamineni ,  Mark V. Raymond ,  Xunyuan Zhang

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535

Abstract: Integrated circuit (IC) structure embodiments and methods of forming them with middle of the line (MOL) contacts that incorporate a protective cap, which provides protection from damage during back end of the line (BEOL) processing. Each MOL contact has a main body in a lower portion of a contact opening. The main body has a liner (e.g., a titanium nitride layer) that lines the lower portion and a metal layer on the liner. The MOL contact also has a protective cap in an upper portion of the contact opening above the first metal layer and extending laterally over the liner to the sidewalls of the contact opening. The protective cap has an optional liner, which is different from the liner in the lower portion, and a metal layer, which is either the same or different than the metal in the main body.

公开(公告)号：US09466530B2

公开(公告)日：2016-10-11

申请号：US14526729

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Tibor Bolom ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76883 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective metal silicide formation process to selectively form a metal silicide layer in the opening and on the conductive contact, depositing at least one conductive material above the selectively formed metal silicide layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials and thereby define a conductive via that is positioned in the opening and conductively coupled to the selectively formed metal silicide layer and to the conductive contact.

Abstract translation: 本文公开的一种说明性方法包括在至少一层绝缘材料中形成开口，从而暴露至少一部分导电接触，进行选择性金属硅化物形成工艺以选择性地形成金属硅化物层 在所述开口中和在所述导电接触件上，在所述选择性形成的金属硅化物层上方沉积至少一种导电材料，以便过度填充所述开口，并进行至少一个平坦化处理，以便去除多余的材料，从而限定导电通孔 其位于开口中并且导电地耦合到选择性形成的金属硅化物层和导电接触。

公开(公告)号：US20160218034A1

公开(公告)日：2016-07-28

申请号：US14729342

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang

IPC: H01L21/768 ,  H01L21/306

CPC classification number: H01L21/76877 ,  H01L21/30625 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes selectively depositing a metal layer overlying a metal line of a metallization layer that is disposed in an ILD layer of dielectric material while an upper surface of the ILD layer that is laterally adjacent to the metal line is exposed. A hard mask layer is formed overlying the upper surface of the ILD layer laterally adjacent to the metal layer. The metal layer is removed to expose the metal line while leaving the hard mask layer intact. An interconnect is formed with the metal line adjacent to the hard mask layer.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括选择性地沉积覆盖金属化层的金属线的金属层，所述金属层设置在介电材料的ILD层中，而ILD层的与金属横向相邻的上表面 线暴露。 在ILD层的与金属层相邻的上表面上形成硬掩模层。 去除金属层以露出金属线，同时使硬掩模层完好无损。 与硬掩模层相邻的金属线形成互连。