公开(公告)号：US09390925B1

公开(公告)日：2016-07-12

申请号：US14572975

申请日：2014-12-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/00 ,  H01L21/225 ,  H01L21/8234 ,  H01L29/161 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/18 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/161

Abstract: Constructing an SiGe fin by: (i) providing an intermediate sub-assembly including a silicon-containing base layer and a silicon-containing first fin structure extending in an upwards direction from the base layer; (ii) refining the sub-assembly by covering at least a portion of the top surface of the base layer and at least a portion of the first and second lateral surfaces of the first fin structure with a pre-thermal-oxidation layer that includes Silicon-Germanium (SiGe); and (iii) further refining the sub-assembly by thermally oxidizing the pre-thermal oxidation layer to migrate Ge content from the pre-thermal-oxidation layer into at least a portion of the base layer and at least a portion of first fin structure.

Abstract translation: 通过以下步骤构造SiGe翅片：（i）提供包括从基底层向上方延伸的含硅基底层和含硅的第一翅片结构的中间子组件; （ii）通过用包括硅的预热氧化层覆盖基层的顶表面的至少一部分和第一鳍结构的第一和第二侧表面的至少一部分来精炼子组件 锗（SiGe）; 和（iii）通过热氧化预热氧化层以使Ge含量从预热氧化层迁移到基层的至少一部分和第一翅片结构的至少一部分中，进一步细化子组件。

公开(公告)号：US09385231B2

公开(公告)日：2016-07-05

申请号：US14530796

申请日：2014-11-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/04 ,  H01L29/08 ,  H01L29/165 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7841 ,  H01L29/78618 ,  H01L29/78654

Abstract: A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain regions are laterally etched to provide recesses for accommodating low-k dielectric material without compromising the contact area between the source/drain regions and their associated contacts. A high-k dielectric layer is provided between the raised source/drain regions and a gate conductor as well as between the gate conductor and a substrate, such as an ETSOI or PDSOI substrate. The structure is usable in electronic devices such as MOSFET devices.

Abstract translation: 包括外延源极和漏极区域的FET结构包括大的接触区域，并且具有低电阻率和低的寄生栅极至源极/漏极电容。 源极和漏极区域被横向蚀刻以提供用于容纳低k电介质材料的凹部，而不损害源极/漏极区域及其相关联的接触之间的接触面积。 高K电介质层设置在凸起的源极/漏极区域和栅极导体之间​​以及栅极导体和诸如ETSOI或PDSOI衬底之类的衬底之间。 该结构可用于诸如MOSFET器件的电子器件中。

公开(公告)号：US09378948B2

公开(公告)日：2016-06-28

申请号：US14672157

申请日：2015-03-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/12 ,  H01L21/02 ,  H01L27/088 ,  H01L21/324 ,  H01L21/84 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L21/02532 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795

Abstract: A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon germanium fins. Such fins are formed by annealing the structure to mix a germanium containing layer with an adjoining crystalline silicon layer. The structure further includes an nFET region including silicon fins formed from the crystalline silicon layer. The germanium containing layer in the nFET region is removed to create a space beneath the crystalline silicon layer in the nFET region. An insulating material is provided within the space. The pFET and nFET regions are electrically isolated by a shallow trench isolation region.

公开(公告)号：US20160181359A1

公开(公告)日：2016-06-23

申请号：US14578523

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa A. Smith

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/304 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02636 ,  H01L21/02647 ,  H01L21/2022 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76248 ,  H01L21/76294 ,  H01L29/0642 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/785

Abstract: A semiconductor structure including: trench-defining layer; an epitaxial layer; and a set of defect-blocking member(s). The trench-defining layer includes a trench surface which defines an elongated interior space called the “trench.” The epitaxial layer is grown epitaxially in the interior space of the trench. Each defect blocking member of the set of defect blocking members: (i) extends from a portion of trench surface into the interior space of the trench; and (ii) is located below a top surface of the epitaxial layer. The defect blocking member(s) are designed to arrest the propagation of generally-longitudinal defects in the epitaxial layer, as it is grown, where the generally-longitudinal defects are defects that propagate at least generally in the elongation direction of the trench.

Abstract translation: 一种半导体结构，包括：沟槽限定层; 外延层; 和一组缺陷阻挡构件。 沟槽限定层包括限定被称为“沟槽”的细长内部空间的沟槽表面。外延层在沟槽的内部空间中外延生长。 该组缺陷阻挡构件的每个缺陷阻挡构件：（i）从沟槽表面的一部分延伸到沟槽的内部空间中; 和（ii）位于外延层的顶表面下方。 缺陷阻挡构件设计成在其生长时阻止外延层中的大致纵向缺陷的传播，其中大致纵向缺陷是至少大体上在沟槽的伸长方向上传播的缺陷。

公开(公告)号：US09373637B2

公开(公告)日：2016-06-21

申请号：US14526767

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L27/06 ,  H01L29/06 ,  H01L29/36 ,  H01L29/417 ,  H01L49/02 ,  H01L21/84 ,  H01L27/13

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/13 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/41783

Abstract: An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material.

公开(公告)号：US20160141368A1

公开(公告)日：2016-05-19

申请号：US14540051

申请日：2014-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic Schepis

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/1054 ,  H01L21/02123 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming one or more tall strained silicon germanium (SiGe) fins on a semiconductor on insulator (SOI) substrate. The fins have a germanium (Ge) concentration which may differ from the Ge concentration within the top layer of the SOI substrate. The difference in Ge concentration between the fins and the top layer of the SOI substrate may range from approximately 10 atomic percent to approximately 40 atomic percent. This Ge concentration differential may be used to tailor a strain on the fins. The strain on the fins may be tailored to increase the critical thickness and allow for a greater height of the fins as compared to conventional strained fins of the same SiGe concentration formed from bulk material.

Abstract translation: 本发明一般涉及半导体器件，更具体地，涉及在绝缘体上半导体（SOI）衬底上形成一个或多个高应变硅锗（SiGe）鳍片的结构和方法。 散热片的锗（Ge）浓度可能与SOI衬底的顶层内的Ge浓度不同。 SOI衬底的翅片和顶层之间的Ge浓度的差可以在约10原子％至约40原子％的范围内。 该Ge浓度差可用于调节鳍片上的应变。 与散装材料形成的相同SiGe浓度的常规应变翅片相比，翅片上的应变可以被调整以增加临界厚度并允许翅片更大的高度。

公开(公告)号：US09343550B2

公开(公告)日：2016-05-17

申请号：US14666469

申请日：2015-03-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/762 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/785

Abstract: A semiconductor device includes an insulator formed within a void to electrically isolate an active fin from an underlying substrate. The void is created by removing a sacrificial portion formed between the substrate and the active fin. The sacrificial portion may be doped to allow for a greater thickness relative to an un-doped portion of substantially similar composition. The doped sacrificial portion thickness may be between 10 nm and 250 nm. The thicker sacrificial portion allows for a thicker insulator so as to provide adequate electrical isolation between the active fin and the substrate. During formation of the void, the active fin may be supported by a gate. The semiconductor structure may also include a bulk region that has at least a maintained portion of the sacrificial portion material.

Abstract translation: 半导体器件包括形成在空隙内的绝缘体，以将活性鳍与下面的衬底电隔离。 通过去除形成在衬底和活性鳍片之间的牺牲部分来产生空隙。 牺牲部分可以被掺杂以允许相对于基本相似组成的未掺杂部分具有更大的厚度。 掺杂的牺牲部分厚度可以在10nm和250nm之间。 较厚的牺牲部分允许较厚的绝缘体，以便在活性鳍片和衬底之间提供足够的电绝缘。 在形成空隙期间，活性翅片可以由浇口支撑。 半导体结构还可以包括具有牺牲部分材料的至少保持部分的主体区域。

公开(公告)号：US09257536B2

公开(公告)日：2016-02-09

申请号：US13867247

申请日：2013-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

IPC: H01L29/66

CPC classification number: H01L29/66795

Abstract: FinFET structures and methods of formation are disclosed. Fins are formed on a bulk substrate. A crystalline insulator layer is formed on the bulk substrate with the fins sticking out of the epitaxial oxide layer. A gate is formed around the fins protruding from the crystalline insulator layer. An epitaxially grown semiconductor region is formed in the source drain region by merging the fins on the crystalline insulator layer to form a fin merging region.

Abstract translation: 公开了FinFET结构和形成方法。 翅片形成在块状基底上。 在散装衬底上形成结晶绝缘体层，翅片从外延氧化物层伸出。 在从结晶绝缘体层突出的翅片周围形成栅极。 通过将结晶绝缘体层上的翅片合并形成翅片合并区域，在源漏区域中形成外延生长的半导体区域。

公开(公告)号：US09246003B2

公开(公告)日：2016-01-26

申请号：US14083517

申请日：2013-11-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Eric C. Harley ,  Yue Ke ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/772 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7842 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor structure may include a semiconductor fin, a gate over the semiconductor fin, a spacer on a sidewall of the gate, an angled recess region in an end of the semiconductor fin beneath the spacer, and a first semiconductor region filling the angled recess. The angled recess may be v-shaped or sigma shaped. The structure may further include a second semiconductor region in contact with the first semiconductor region and the substrate. The structure may be formed by forming a gate above a portion of the semiconductor fin on a substrate, forming a spacer on a sidewall of the gate; removing a portion of the semiconductor fin not covered by the spacer or the gate to expose a sidewall of the fin, etching the sidewall of the fin to form an angled recess region beneath the spacer, and filling the angled recess region with a first epitaxial semiconductor region.

Abstract translation: 半导体结构可以包括半导体鳍片，半导体鳍片上的栅极，栅极的侧壁上的间隔物，在间隔物下方的半导体鳍片的端部中的成角度的凹陷区域以及填充成角度的凹部的第一半导体区域。 成角度的凹槽可以是v形或西格玛形。 该结构还可以包括与第一半导体区域和衬底接触的第二半导体区域。 该结构可以通过在衬底上形成半导体翅片的一部分上方的栅极形成，在栅极的侧壁上形成间隔物; 除去未被间隔物或栅极覆盖的半导体鳍片的一部分以暴露翅片的侧壁，蚀刻翅片的侧壁以在间隔物下方形成倾斜的凹陷区域，并用第一外延半导体填充成角度的凹陷区域 地区。

公开(公告)号：US09219139B2

公开(公告)日：2015-12-22

申请号：US14081320

申请日：2013-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/20

CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/20 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90°+/−5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures.

Abstract translation: 一种半导体器件，包括在衬底表面上的至少两个鳍结构和存在于所述至少两个鳍结构上的功能栅结构。 功能栅极结构包括至少一个与至少两个鳍结构的侧壁直接接触的栅极电介质，以及至少一个栅极电介质上的至少一个栅极导体。 栅极结构的侧壁基本上垂直于衬底表面的上表面，其中由栅极结构的侧壁限定的平面和由衬底表面的上表面限定的平面以90°±/ -5°。 外延半导体材料与至少两个翅片结构直接接触。