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公开(公告)号：US20080079105A1
公开(公告)日：2008-04-03
申请号：US11904648
申请日：2007-09-27
IPC分类号： H01L31/0203 , H01L21/02
CPC分类号： H01L27/14618 , H01L24/97 , H01L27/14683 , H01L2224/48091 , H01L2224/48227 , H01L2224/97 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082 , H01L2924/15311 , H01L2924/16195 , H01L2224/85 , H01L2924/00014
摘要： A sensor-type package and a fabrication method thereof are provided. A sensor-type chip is mounted on a substrate and is electrically connected to the substrate via bonding wires. A light-pervious body is attached to the sensor-type chip, and has one surface covered with a covering layer and another surface formed with an adhesive layer. An encapsulant encapsulates the light-pervious body. As an adhesive force between the covering layer and the encapsulant is greater than that between the covering layer and the light-pervious body, the covering layer and a portion of the encapsulant located on the covering layer can be concurrently removed, such that the light-pervious body is exposed and light can pass through the light-pervious body to be captured by the sensor-type chip. The above arrangement eliminates the need of using a dam structure as in the prior art and provides a compact sensor-type package with improved fabrication reliability.
摘要翻译： 提供了传感器型封装及其制造方法。 传感器型芯片安装在基板上，并通过接合线与基板电连接。 透光体附着在传感器型芯片上，其一个表面被覆盖层和形成有粘合剂层的另一表面覆盖。 密封剂封装透光体。 由于覆盖层和密封剂之间的粘合力大于覆盖层和透光体之间的粘合力，所以可以同时去除位于覆盖层上的覆盖层和密封剂的一部分， 透光体被曝光，光可以通过透光体，由传感器型芯片捕获。 上述布置消除了如现有技术中使用坝结构的需要，并且提供了具有改进的制造可靠性的紧凑型传感器型封装。
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公开(公告)号：US07348211B2
公开(公告)日：2008-03-25
申请号：US11117158
申请日：2005-04-27
申请人： Ying-Ren Lin , Ho-Yi Tsai , Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Ying-Ren Lin , Ho-Yi Tsai , Chien-Ping Huang , Cheng-Hsu Hsiao
CPC分类号： H01L21/565 , H01L21/568 , H01L23/3128 , H01L24/48 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for fabricating semiconductor packages is proposed. A plurality of substrates each having a chip thereon are prepared. Each substrate has similar length and width to the predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. Each opening is larger in length and width than the substrate. The substrates are positioned in the corresponding openings, and gaps between the substrates and the carrier are sealed. A molding process is performed to form an encapsulant over each opening to encapsulate the chip. An area on the carrier covered by the encapsulant is larger in length and width than the opening. After performing a mold-releasing process, a plurality of the semiconductor packages are formed by a singulation process to cut along substantially edges of each substrate according to the predetermined size of the semiconductor package. A waste of substrate material is avoided.
摘要翻译： 提出了制造半导体封装的方法。 制备各自具有芯片的多个基板。 每个衬底具有与半导体封装的预定长度和宽度相似的长度和宽度。 制备具有多个开口的载体。 每个开口的长度和宽度大于衬底。 基板定位在相应的开口中，基板和载体之间的间隙被密封。 执行成型工艺以在每个开口上形成密封剂以封装芯片。 由密封剂覆盖的载体上的区域的长度和宽度大于开口的宽度。 在执行脱模工艺之后，通过单片化工艺形成多个半导体封装，以根据半导体封装的预定尺寸沿着每个衬底的大致边缘切割。 避免了衬底材料的浪费。
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公开(公告)号：US20080017983A1
公开(公告)日：2008-01-24
申请号：US11880467
申请日：2007-07-20
申请人： Yuan-Lin Tzeng , Nai-Hao Kao , Jeng-Yuan Lai , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Yuan-Lin Tzeng , Nai-Hao Kao , Jeng-Yuan Lai , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L23/48
CPC分类号： H01L21/563 , H01L24/31 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83951 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01082 , H01L2924/19041 , H01L2924/19043 , H01L2924/3011 , H01L2924/351 , H01L2924/00
摘要： The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.
摘要翻译： 本发明公开了一种倒装芯片半导体封装及其芯片载体。 芯片载体包括围绕芯片安装区域形成的凹槽。 槽可以沿着芯片安装区域的周边或其拐角处形成。 凹槽填充有低杨氏模量的填料，以吸收和消除热应力，从而防止底部填充物和安装在芯片安装区域上的倒装芯片之间的分层。
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公开(公告)号：US20070273026A1
公开(公告)日：2007-11-29
申请号：US11701767
申请日：2007-02-02
申请人： Hsieh-Tsung Tien , Wen-Jung Chiang , Yu-Po Wang , Cheng-Hsu Hsiao , Sen-Yen Yang
发明人： Hsieh-Tsung Tien , Wen-Jung Chiang , Yu-Po Wang , Cheng-Hsu Hsiao , Sen-Yen Yang
IPC分类号： H01L23/488
CPC分类号： H01L23/49827 , H01L23/64 , H01L2223/6638 , H01L2924/0002 , H01L2924/3011 , H05K1/0245 , H05K1/0251 , H05K1/114 , H05K3/429 , H05K2201/09236 , H05K2201/09636 , H05K2201/09718 , H01L2924/00
摘要： A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.
摘要翻译： 提供了一种半导体封装基板，其包括其中形成有多个导电通孔的基板主体，其中至少两个相邻的导电通孔形成为差分对，每个导体通孔在其一端形成有球垫; 以及形成在所述基板主体中的至少一个电气集成层，并且具有与形成为所述差动对的两个相邻的导电通孔对应的开口及其球垫。 因此，可以通过开口来扩大导电通孔和电气集成层之间的间隔以及球垫之间的间隔，从而平衡阻抗匹配。
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65.发明申请Method for fabricating wafer level semiconductor package with build-up layer 有权用于制造具有堆积层的晶片级半导体封装的方法公开(公告)号：US20070034998A1
公开(公告)日：2007-02-15
申请号：US11580560
申请日：2006-10-12
IPC分类号： H01L23/02
CPC分类号： H01L21/6835 , H01L21/568 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/351 , H01L2924/3511 , H01L2224/82 , H01L2924/00
摘要： A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.
摘要翻译： 提供具有积层的晶片级半导体封装，其包括具有用于接收其中的半导体芯片的通孔的玻璃框架，填充在形成在半导体芯片和玻璃框架之间的空间内的低模量缓冲材料， 形成在所述玻璃框架和所述半导体芯片上的堆积层，使得所述积层层电连接到所述半导体芯片，以及安装在所述积层层上的多个导电元件，使得所述半导体芯片电连接 到外部设备。 通过使用玻璃框架和低模量缓冲材料，由此获得的晶片级半导体封装没有翘曲，芯片裂纹和分层问题，并且其可靠性得到提高。 还提供了一种用于制造晶片级半导体封装的方法。
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公开(公告)号：US20060292741A1
公开(公告)日：2006-12-28
申请号：US11471516
申请日：2006-06-21
IPC分类号： H01L21/00
CPC分类号： H01L23/3128 , H01L21/561 , H01L23/4334 , H01L24/48 , H01L24/97 , H01L2224/16 , H01L2224/48227 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/351 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A heat-dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted and electrically connected to a substrate. A heat-dissipating structure includes a heat sink and at least one supporting portion, wherein the supporting portion is attached to the substrate at a position outside a predetermined package area for the semiconductor package, and the semiconductor chip is disposed under the heat sink. An encapsulant is formed on the substrate to encapsulate the semiconductor chip and the heat-dissipating structure, wherein a projection area of the encapsulant on the substrate is larger in size than the predetermined package area. A cutting process is performed along edges of the predetermined package area to remove parts of the encapsulant, the supporting portion and the substrate, which are located outside the predetermined package area, so as to form the semiconductor package integrated with the heat-dissipating structure.
摘要翻译： 提供散热半导体封装及其制造方法。 半导体芯片安装并电连接到基板。 散热结构包括散热器和至少一个支撑部分，其中支撑部分在用于半导体封装的预定封装区域外的位置处附接到基板，并且半导体芯片设置在散热器下方。 在基板上形成密封剂以封装半导体芯片和散热结构，其中密封剂在基板上的投影面积大于预定封装面积。 沿着预定包装区域的边缘进行切割处理以去除位于预定包装区域外部的密封剂，支撑部分和基底的部分，以形成与散热结构集成的半导体封装。
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公开(公告)号：US20060103014A1
公开(公告)日：2006-05-18
申请号：US11232612
申请日：2005-09-21
申请人： Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Chien-Ping Huang , Cheng-Hsu Hsiao
IPC分类号： H01L23/34
CPC分类号： H01L24/97 , H01L23/3128 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L2224/16 , H01L2224/16225 , H01L2224/16245 , H01L2224/45144 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/73253 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2224/85 , H01L2224/81 , H01L2224/83 , H01L2224/05599 , H01L2224/0401
摘要： A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; an encapsulant formed on the chip carrier and for encapsulating the chip, with a non-active surface of the chip being exposed from the encapsulant; and a heat spreader having a hollow portion and attached to the encapsulant, wherein the chip is received in the hollow portion and the non-active surface of the chip is completely exposed to the hollow portion, such that heat generated by the chip can be directly dissipated out of the package structure. The present invention also provides a method for fabricating the heat dissipating package structure.
摘要翻译： 散热封装结构包括芯片载体; 安装并电连接到芯片载体的半导体芯片; 形成在所述芯片载体上并用于封装所述芯片的密封剂，所述芯片的非活性表面从所述密封剂暴露出来; 以及具有中空部分并附着到密封剂的散热器，其中芯片被容纳在中空部分中，并且芯片的非活动表面完全暴露于中空部分，使得芯片产生的热量可以直接 从包装结构中消散掉。 本发明还提供一种制造散热封装结构的方法。
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公开(公告)号：US07019406B2
公开(公告)日：2006-03-28
申请号：US10635168
申请日：2003-08-05
申请人： Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Chien-Ping Huang , Cheng-Hsu Hsiao
CPC分类号： H01L24/97 , H01L23/3128 , H01L23/36 , H01L23/4334 , H01L23/5389 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2224/32245 , H01L2224/73267 , H01L2224/83385 , H01L2224/92224 , H01L2224/92244 , H01L2224/97 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/15159 , H01L2924/15311 , H01L2224/82 , H01L2224/83 , H01L2924/00
摘要： A thermally enhanced semiconductor package and a fabrication method thereof are provided. A plurality of conductive bumps are formed on bond pads on an active surface of a chip. A heat sink is attached to an inactive surface of the chip and has a surface area larger than that of the chip. An encapsulation body encapsulates the heat sink, chip and conductive bumps, while exposing a bottom or surfaces, not for attaching the chip, of the heat sink and ends of the conductive bumps outside. A plurality of conductive traces are formed on the encapsulation body and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with a plurality of openings for exposing predetermined portions of the conductive traces. A solder ball is implanted on each exposed portion of the conductive traces.
摘要翻译： 提供一种热增强型半导体封装及其制造方法。 在芯片的有源表面上的接合焊盘上形成多个导电凸块。 散热器附着在芯片的非活性表面上，其表面积大于芯片的表面积。 封装体封装散热器，芯片和导电凸块，同时暴露散热片的底部或表面，而不是将散热片和导电凸块的端部外露。 多个导电迹线形成在封装主体上并电连接到导电凸块的端部。 焊接掩模层施加在导电迹线上并形成有多个用于暴露导电迹线的预定部分的开口。 在导电迹线的每个暴露部分上注入焊球。
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公开(公告)号：US06989296B2
公开(公告)日：2006-01-24
申请号：US10844877
申请日：2004-05-12
IPC分类号： H01L21/44
CPC分类号： H01L23/055 , H01L21/50 , H01L23/10 , H01L24/45 , H01L24/48 , H01L24/97 , H01L27/14618 , H01L27/14683 , H01L2224/16 , H01L2224/45144 , H01L2224/48091 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/15173 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2224/05599 , H01L2924/00
摘要： A fabrication method of a semiconductor package with a photosensitive chip is provided. A substrate having a core is prepared. An interposer is mounted on the substrate, with a peripheral portion of the substrate exposed from the interposer. A molding process is performed and the substrate is clamped between an upper mold and a lower mold, with the interposer received in an upwardly-recessed cavity of the upper mold. A molding compound is injected into the upwardly-recessed cavity to form a dam on the peripheral portion of the substrate. Then the upper and lower molds and the interposer are removed from the substrate to expose area covered by the interposer on the substrate. At least one photosensitive chip is mounted on the exposed area of the substrate. A lid seals the dam such that the chip is received in a space defined by the substrate, the dam and the lid.
摘要翻译： 提供了具有感光芯片的半导体封装的制造方法。 制备具有芯的衬底。 插入器安装在衬底上，衬底的周边部分从插入件露出。 进行成型工艺，并且将基板夹在上模具和下模具之间，其中插入件容纳在上模具的向上凹入的空腔中。 将模塑料注入到上凹腔中以在基材的周边部分上形成坝。 然后将上模和下模和插入件从基板上移除以露出基板上由插入件覆盖的区域。 至少一个感光芯片安装在基板的暴露区域上。 盖子密封大坝，使得芯片被容纳在由基板，坝和盖子限定的空间中。
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公开(公告)号：US20050287707A1
公开(公告)日：2005-12-29
申请号：US11117158
申请日：2005-04-27
申请人： Ying-Ren Lin , Ho-Yi Tsai , Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Ying-Ren Lin , Ho-Yi Tsai , Chien-Ping Huang , Cheng-Hsu Hsiao
CPC分类号： H01L21/565 , H01L21/568 , H01L23/3128 , H01L24/48 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for fabricating semiconductor packages is proposed. A plurality of substrates each having a chip thereon are prepared. Each substrate has similar length and width to the predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. Each opening is larger in length and width than the substrate. The substrates are positioned in the corresponding openings, and gaps between the substrates and the carrier are sealed. A molding process is performed to form an encapsulant over each opening to encapsulate the chip. An area on the carrier covered by the encapsulant is larger in length and width than the opening. After performing a mold-releasing process, a plurality of the semiconductor packages are formed by a singulation process to cut along substantially edges of each substrate according to the predetermined size of the semiconductor package. A waste of substrate material is avoided.
摘要翻译： 提出了制造半导体封装的方法。 制备各自具有芯片的多个基板。 每个衬底具有与半导体封装的预定长度和宽度相似的长度和宽度。 制备具有多个开口的载体。 每个开口的长度和宽度大于衬底。 基板定位在相应的开口中，基板和载体之间的间隙被密封。 执行成型工艺以在每个开口上形成密封剂以封装芯片。 由密封剂覆盖的载体上的区域的长度和宽度大于开口的宽度。 在执行脱模工艺之后，通过单片化工艺形成多个半导体封装，以根据半导体封装的预定尺寸沿着每个衬底的大致边缘切割。 避免了衬底材料的浪费。
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