公开(公告)号：US09761665B2

公开(公告)日：2017-09-12

申请号：US15157448

申请日：2016-05-18

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Stefan Decker ,  Norbert Krischke ,  Christoph Kadow

IPC: H01L27/148 ,  H01L29/768 ,  H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L29/105 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66537 ,  H01L29/78

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

公开(公告)号：US20160377689A1

公开(公告)日：2016-12-29

申请号：US15049923

申请日：2016-02-22

Applicant: Infineon Technologies AG

Inventor： Giuliano Angelo Babulano ,  Jens Oetjen ,  Liu Chen ,  Toni Salminen ,  Stefan Mieslinger ,  Markus Dinkel ,  Martin Gruber ,  Franz Jost ,  Thorsten Meyer ,  Rainer Schaller

IPC: G01R33/00 ,  G01R33/09

CPC classification number: G01R33/0047 ,  G01R33/091 ,  H01L43/02 ,  H01L43/08 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/4903

Abstract: An interconnect module includes a metal clip having a first end section, a second end section and a middle section extending between the first and the second end sections. The first end section is configured for external attachment to a bare semiconductor die or packaged semiconductor die attached to a carrier or to a metal region of the carrier. The second end section is configured for external attachment to a different metal region of the carrier or to a different semiconductor die or packaged semiconductor die attached to the carrier. The module further includes a magnetic field sensor secured to the metal clip. The magnetic field sensor is operable to sense a magnetic field produced by current flowing through the metal clip. The interconnect module can be used to form a direct electrical connection between components and/or metal regions of a carrier to which the module is attached.

Abstract translation: 互连模块包括具有第一端部分，第二端部部分和在第一和第二端部部分之间延伸的中间部分的金属夹。 第一端部部分被配置为外部连接到附接到载体或载体的金属区域的裸半导体管芯或封装的半导体管芯。 第二端部构造成用于外部附接到载体的不同金属区域或者附接到载体的不同的半导体管芯或封装的半导体管芯。 该模块还包括固定到金属夹的磁场传感器。 磁场传感器可操作以感测由流过金属夹的电流产生的磁场。 互连模块可以用于在模块附接到的载体的部件和/或金属区域之间形成直接电连接。

公开(公告)号：US20160343616A1

公开(公告)日：2016-11-24

申请号：US15226260

申请日：2016-08-02

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Jens Pohl

IPC: H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/488 ,  H01L23/49861 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive.

Abstract translation: 半导体器件包括芯片，至少一个元件，电耦合到芯片，至少部分覆盖至少一个元件的粘合剂，以及至少部分地覆盖芯片和粘合剂的模具材料。

公开(公告)号：US20160093728A1

公开(公告)日：2016-03-31

申请号：US14868857

申请日：2015-09-29

Applicant: Infineon Technologies AG

Inventor： Stefan Decker ,  Sven Lanzerstorfer ,  Thorsten Meyer ,  Robert Zink

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811

Abstract: A semiconductor device comprises a semiconductor body. The semiconductor body comprises insulated gate field effect transistor cells. At least one of the insulated gate field effect transistor cells comprises a source zone of a first conductivity type, a body zone of a second, complementary conductivity type, a drift zone of the first conductivity type, and a trench gate structure extending into the semiconductor body through the body zone along a vertical direction. The trench gate structure comprises a gate electrode separated from the semiconductor body by a trench dielectric. The trench dielectric comprises a source dielectric part interposed between the gate electrode and the source zone and a gate dielectric part interposed between the gate electrode and the body zone. The ratio of a maximum thickness of the source dielectric part along a lateral direction and the minimum thickness of the gate dielectric part along the lateral direction is at least 1.5.

Abstract translation: 半导体器件包括半导体本体。 半导体本体包括绝缘栅场效应晶体管单元。 绝缘栅场效应晶体管单元中的至少一个包括第一导电类型的源极区，第二互补导电类型的体区，第一导电类型的漂移区和延伸到半导体中的沟槽栅结构 身体通过身体区域沿垂直方向。 沟槽栅极结构包括通过沟槽电介质与半导体本体分离的栅电极。 沟槽电介质包括介于栅极电极和源极区之间的源极介电部分和介于栅极电极和主体区域之间的栅极电介质部分。 源电介质部分沿横向方向的最大厚度与栅电介质部分沿横向方向的最小厚度之比至少为1.5。

公开(公告)号：US12154886B2

公开(公告)日：2024-11-26

申请号：US17502163

申请日：2021-10-15

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Martin Gruber ,  Thorsten Scharf

IPC: H01L23/02 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package is disclosed. In one example, the package includes a non-power chip including a first electrical contact arranged at a first main surface of the non-power chip. The semiconductor package further includes a power chip comprising a second electrical contact arranged at a second main surface of the power chip. A first electrical redistribution layer coupled to the first electrical contact and a second electrical redistribution layer coupled to the second electrical contact. When measured in a first direction vertical to at least one of the first main surface or the second main surface, a maximum thickness of at least a section of the first electrical redistribution layer is smaller than a maximum thickness of the second electrical redistribution layer.

公开(公告)号：US12094842B2

公开(公告)日：2024-09-17

申请号：US16360387

申请日：2019-03-21

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Walter Hartner ,  Maciej Wojnowski

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/66 ,  H01L29/06 ,  H01Q1/22

CPC classification number: H01L23/66 ,  H01L23/3114 ,  H01L23/5226 ,  H01L23/5227 ,  H01L24/19 ,  H01L24/20 ,  H01L29/0657 ,  H01Q1/2283 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/81203 ,  H01L2924/00014 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2224/83825 ,  H01L2924/00014 ,  H01L2224/83102 ,  H01L2924/00014

Abstract: A semiconductor device includes a semiconductor die having an active main surface and an opposite main surface opposite the active main surface. The semiconductor device further includes an antenna arranged on the active main surface of the semiconductor die and a recess arranged on the opposite main surface of the semiconductor die. The recess is arranged over the antenna.

公开(公告)号：US11862582B2

公开(公告)日：2024-01-02

申请号：US17502084

申请日：2021-10-15

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Thomas Bemmerl ,  Martin Gruber ,  Martin Richard Niessner

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/564 ,  H01L21/481 ,  H01L21/4828 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49541 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/73265 ,  H01L2224/92247

Abstract: A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, an encapsulant encapsulating at least part of the electronic component and at least part of the carrier and having a bottom side at a first vertical level. At least one lead is electrically coupled with the electronic component and comprising a first lead portion being encapsulated in the encapsulant and a second lead portion extending out of the encapsulant at the bottom side of the encapsulant. A functional structure at the bottom side extends up to a second vertical level different from the first vertical level.

公开(公告)号：US11515244B2

公开(公告)日：2022-11-29

申请号：US16748049

申请日：2020-01-21

Applicant: Infineon Technologies AG

Inventor： Bun Kian Tay ,  Mei Yih Goh ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Thorsten Scharf ,  Chee Voon Tan

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

公开(公告)号：US20220285550A1

公开(公告)日：2022-09-08

申请号：US17824198

申请日：2022-05-25

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andreas Meiser ,  Hans-Peter Lang ,  Thorsten Meyer ,  Peter Irsigler

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L23/48 ,  H01L27/06 ,  H01L29/861 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/45 ,  H01L21/74 ,  H01L29/423

Abstract: A method of manufacturing a semiconductor body includes forming a pattern at a first side of a substrate, forming a semiconductor layer on the first side of the substrate, attaching the substrate and the semiconductor layer to a carrier via a surface of the semiconductor layer, and removing the substrate from a second side opposite to the first side.

公开(公告)号：US11264356B2

公开(公告)日：2022-03-01

申请号：US16842417

申请日：2020-04-07

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Thomas Behrens ,  Andreas Grassmann ,  Martin Gruber ,  Thorsten Scharf

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

Abstract: A method of manufacturing packages is disclosed. In one example, the method comprises providing an electrically conductive sheet being continuous at least in a mounting region, mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet and forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet. The second main surfaces oppose the first main surfaces. After the forming, structuring the sheet.