公开(公告)号：US20210050941A1

公开(公告)日：2021-02-18

申请号：US17086085

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Per E. Fornberg ,  Tal Israeli ,  Zuoguo Wu

IPC: H04L1/00 ,  H03M13/09

Abstract: Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.

公开(公告)号：US10854548B2

公开(公告)日：2020-12-01

申请号：US16236136

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Debendra Das Sharma ,  Adel A. Elsherbini ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065

Abstract: Inter-die passive interconnects are lengthened while locating I/O circuitry away from die edge, such that passive interconnect length is agglomerated toward the die edge, and inter-die communication is expedited.

公开(公告)号：US20200319957A1

公开(公告)日：2020-10-08

申请号：US16779391

申请日：2020-01-31

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Robert G. Blankenship ,  Mahesh Wagh ,  Zuoguo Wu

IPC: G06F11/10 ,  H04L29/06 ,  H04L1/00 ,  H04L1/20 ,  G06F13/16

Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

公开(公告)号：US20200211965A1

公开(公告)日：2020-07-02

申请号：US16236136

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Debendra Das Sharma ,  Adel A. Elsherbini ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: Inter-die passive interconnects are lengthened while locating I/O circuitry away from die edge, such that passive interconnect length is agglomerated toward the die edge, and inter-die communication is expedited.

公开(公告)号：US10678736B2

公开(公告)日：2020-06-09

申请号：US15761401

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Zuoguo Wu ,  Mahesh Wagh ,  Mohiuddin M. Mazumder ,  Venkatraman Iyer ,  Jeff C. Morriss

IPC: G06F13/366 ,  G06F13/40 ,  H01L25/065 ,  G06F13/42 ,  H01L23/538

Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

公开(公告)号：US20200067526A1

公开(公告)日：2020-02-27

申请号：US16563496

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Debendra Das Sharma ,  Md. Mohiuddin Mazumder ,  Subas Bastola ,  Kai Xiao

IPC: H03M13/11 ,  G06F13/38 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42

Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

公开(公告)号：US09935063B2

公开(公告)日：2018-04-03

申请号：US15201375

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Yu Amos Zhang ,  Jihwan Kim ,  Ajay Balankutty ,  Anupriya Sriramulu ,  MD. Mohiuddin Mazumder ,  Frank O'Mahony ,  Zuoguo Wu ,  Kemal Aygun

IPC: H01L23/00 ,  H01L23/64 ,  H02H9/04 ,  H01L27/02 ,  H01L23/66

CPC classification number: H01L23/645 ,  H01L23/66 ,  H01L27/0248 ,  H01L27/0288 ,  H02H9/046

Abstract: Integrated circuit (IC) chip “on-die” inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a surface contact of the chip. Such inductor structures may include a first data signal inductor having (1) a second end electrically coupled to an electrostatic discharge (ESD) circuit and a capacitance value of that circuit, and (2) a first end electrically coupled to a the data signal surface contact and to a capacitance value at that contact; and a second data signal inductor having (1) a second end electrically coupled to the data signal circuit and a capacitance value of that circuit, (2) a first end electrically coupled to the second end of the first data signal inductor, and to the capacitance value of the ESD circuit. Inductor values of the first and second inductors may be selected to cancel out the capacitance values to improve signaling.

公开(公告)号：US20170235701A1

公开(公告)日：2017-08-17

申请号：US15503097

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Akshay Pethe ,  Mahesh Wagh ,  David Harriman ,  Su Wei Lim ,  Debendra Das Sharma ,  Daniel Froelich ,  Venkatraman Iyer ,  James Jaussi ,  Zuoguo Wu

IPC: G06F13/42 ,  G06F13/38

CPC classification number: G06F13/4286 ,  G06F13/385 ,  G06F13/4027 ,  G06F2213/0042 ,  G06F2213/4002

Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.

公开(公告)号：US09692402B2

公开(公告)日：2017-06-27

申请号：US14583139

申请日：2014-12-25

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Zuoguo Wu ,  Venkatraman Iyer ,  Gerald S. Pasdast ,  Todd A. Hinck ,  David M. Lee ,  Narasimha R. Lanka

IPC: G06F1/04 ,  H03K5/26 ,  G01R31/04 ,  H03L9/00

CPC classification number: H03K5/26 ,  G01R31/041 ,  G06F1/3296 ,  G06F13/4291 ,  H03K5/131 ,  H03L9/00

Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

公开(公告)号：US20170019105A1

公开(公告)日：2017-01-19

申请号：US14865682

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kai Xiao ,  Zuoguo Wu ,  Venkatraman Iyer

IPC: H03K19/0175 ,  H03K5/08

CPC classification number: H03K19/017509 ,  G06F13/00 ,  H03K5/08 ,  H04L25/0272

Abstract: A redriver device is provided to receive signals from a first device and forward the signals to a second device on a differential link. Detection circuitry is provided to detect presence of the second device on the link by detecting a pulldown voltage generated from termination of the second device on the link, and pulldown relay circuitry is provided to generate an emulated version of the pulldown voltage of the second device on pins to connect to the first device in response to detecting presence of the second device on the link.

Abstract translation: 提供转接装置以从第一装置接收信号，并将信号转发到差分链路上的第二装置。 提供检测电路以通过检测从链路上的第二设备的终止产生的下拉电压来检测链路上的第二设备的存在，并且提供下拉继电器电路以产生第二设备的下拉电压的仿真版本 以响应于检测到链路上的第二设备的存在而连接到第一设备的引脚。