公开(公告)号：US10019312B2

公开(公告)日：2018-07-10

申请号：US15583019

申请日：2017-05-01

Applicant: International Business Machines Corporation

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC: G06F11/10 ,  G06F3/06 ,  H03M13/15 ,  H03M13/19

CPC classification number: G06F11/1044 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0766 ,  G06F11/0772 ,  G06F11/0793 ,  G06F11/1008 ,  G06F11/1024 ,  G06F11/1048 ,  H03M13/1515 ,  H03M13/19

Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

公开(公告)号：US09996414B2

公开(公告)日：2018-06-12

申请号：US15207679

申请日：2016-07-12

Applicant: International Business Machines Corporation

Inventor： Edgar R. Cordero ,  Marc A. Gollub ,  Warren E. Maule ,  Lucas W. Mulkey ,  Anuwat Saetow

IPC: G06F11/10

CPC classification number: G06F11/1004 ,  G06F11/10

Abstract: An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM from a memory controller and executing error checking logic based on the data. The error checking logic detects an error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached. The error condition is communicated to the memory controller in response to determining that detecting the error condition does not cause the error threshold to be reached.

公开(公告)号：US09940457B2

公开(公告)日：2018-04-10

申请号：US14621506

申请日：2015-02-13

Applicant: International Business Machines Corporation

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC: G06F21/55 ,  G06F11/07 ,  G11C7/24 ,  G11C11/40 ,  G11C29/04

CPC classification number: G06F21/554 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0793 ,  G06F2221/034 ,  G11C7/24 ,  G11C11/40 ,  G11C2029/0411

Abstract: Embodiments of the present disclosure provide a method, computer program product, and system for monitoring a dynamic random-access memory (DRAM) device to detect and respond to a cryogenic attack. A processor receives a set of memory information about a DRAM device. The processor then determines a set of error indicators by processing the memory information using a set of decision parameters. The error indicators are then compared to an attack syndrome to determine if the DRAM is experiencing a cryogenic attack. If the DRAM is experiencing a cryogenic attack, access to the DRAM device is disabled.

公开(公告)号：US20180075887A1

公开(公告)日：2018-03-15

申请号：US15815691

申请日：2017-11-16

Applicant: International Business Machines Corporation

Inventor： John S. Bialas, JR. ,  David D. Cadigan ,  Stephen P. Glancy ,  Warren E. Maule ,  Gary A. Van Huben

IPC: G11C7/22 ,  G11C29/50 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  G11C29/50012 ,  G11C2029/5004 ,  G11C2207/2254

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

公开(公告)号：US09734008B2

公开(公告)日：2017-08-15

申请号：US14724901

申请日：2015-05-29

Applicant: International Business Machines Corporation

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC: G06F11/10 ,  G06F11/08 ,  G06F3/06 ,  G11C29/52 ,  G11C7/10 ,  G11C29/04

CPC classification number: G06F11/1008 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/08 ,  G06F11/1032 ,  G06F11/1048 ,  G06F11/106 ,  G06F11/1072 ,  G06F11/1076 ,  G11C7/1006 ,  G11C7/1051 ,  G11C29/52 ,  G11C2029/0411

Abstract: A memory management system and method of managing output data resulting from a memory device storing raw data and error correction coding (ECC) bits are described. The system includes a controller to receive a read command and control a memory device based on the read command, the memory device to store raw data and error correction coding (ECC) bits and output the raw data and the ECC bits corresponding with memory addresses specified in the read command, and an ECC decoder to output an error vector associated with the memory addresses based on the raw data and the ECC bits corresponding with the memory addresses output by the memory device, the error vector associated with the memory addresses indicating errors in the raw data corresponding with the memory addresses. The system also includes a multiplexer (MUX) to output the error vector based on a selection indicated in the read command.

公开(公告)号：US09684555B2

公开(公告)日：2017-06-20

申请号：US14842917

申请日：2015-09-02

Applicant: International Business Machines Corporation

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC: H03M13/00 ,  G06F11/07

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/52 ,  G11C2029/0411

Abstract: A correctable memory error may be identified at a first address within a memory device. Based on at least the identifying, a first correctable memory error count may be updated from a first quantity to a second quantity. The second quantity may be determined to exceed or not exceed a threshold. In response to the determining, the first correctable memory error count of the second quantity may be: converted to a third quantity and reported to a host device accordingly, reported to a host device, or not reported to a host device.

公开(公告)号：US20160328291A1

公开(公告)日：2016-11-10

申请号：US14751382

申请日：2015-06-26

Applicant: International Business Machines Corporation

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1004 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/00 ,  G06F11/1048 ,  G06F11/1076 ,  G06F12/00 ,  G06F13/00

Abstract: Classifying memory errors may include accessing data from a location within a memory array of a memory device. The memory array may include at least one bit field to store memory error classification information. One or more memory errors in the data may be determined. One or more memory errors may further be classified. In response to the classifying, memory error classification information may be stored as one or more bit values within the bit field.

Abstract translation: 分类存储器错误可以包括从存储器设备的存储器阵列内的位置访问数据。 存储器阵列可以包括用于存储存储器错误分类信息的至少一个位字段。 可以确定数据中的一个或多个存储器错误。 可以进一步分类一个或多个存储器错误。 响应于分类，存储器错误分类信息可以作为位字段中的一个或多个位值存储。

公开(公告)号：US09454422B2

公开(公告)日：2016-09-27

申请号：US14168460

申请日：2014-01-30

Applicant: International Business Machines Corporation

Inventor： Paul W. Coteus ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Luis A. Lastras-Montano ,  Warren E. Maule ,  Vipinchandra Patel

IPC: G11C29/00 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/0772 ,  G06F11/073 ,  G06F11/1048

Abstract: Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.

Abstract translation: 可以在片上存储器中执行错误检查和校正（ECC），其中错误由控制器而不是片上存储器校正。 可以标记控制器以示出已经发生错误以及其在存储器中发生的位置。 控制器可以访问与错误相关联的ECC位，并可能修复不正确的数据。 可以与存储器的读取操作并行地进行错误检查，以便降低延迟。

公开(公告)号：US20160036466A1

公开(公告)日：2016-02-04

申请号：US14446922

申请日：2014-07-30

Applicant: International Business Machines Corporation

Inventor： John K. DeBrosse ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Rona Yaari

IPC: H03M13/35 ,  G06F11/10

CPC classification number: H03M13/353 ,  G06F11/1008 ,  G06F11/1048 ,  G06F11/1068 ,  G11C11/4076 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/09

Abstract: According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.

公开(公告)号：US20150357033A1

公开(公告)日：2015-12-10

申请号：US14466335

申请日：2014-08-22

Applicant: International Business Machines Corporation

Inventor： Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC: G11C13/00

CPC classification number: G11C13/0026 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/12 ,  G11C7/18 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/78 ,  G11C2213/79

Abstract: Embodiments of the present disclosure describe a device and methods of accessing the device. The device can include a plurality of memory cells, each cell including a plurality of resistive memory components each designed to store data as resistance and an access transistor configured to control access to the plurality of resistive memory components. A wordline is configured to enable access to the set of resistor memory components by enabling the access transistor. A plurality of bitlines are each connected to a respective and different set of resistive memory components from each of the plurality of memory cells. A bitline controller is configured to access the plurality of resistive memory components by applying a first voltage to a first set of the plurality of bitlines and a second voltage to a second set of bitlines.

Abstract translation: 本公开的实施例描述了访问设备的设备和方法。 该设备可以包括多个存储器单元，每个单元包括多个电阻存储器组件，每个电阻存储器组件被设计为将数据存储为电阻，并且存取晶体管被配置为控制对多个电阻存储器组件的访问。 字线被配置为通过启用存取晶体管来访问该组电阻器存储器组件。 多个位线各自连接到来自多个存储器单元中的每一个的相应且不同的电阻性存储器组件集合。 位线控制器被配置为通过将第一电压施加到多个位线的第一组并且将第二电压施加到第二组位线来访问多个电阻性存储器组件。