公开(公告)号：US20180342532A1

公开(公告)日：2018-11-29

申请号：US15777086

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Aaron D. LILAK

IPC: H01L27/11582 ,  H01L27/108 ,  G11C11/402

CPC classification number: H01L27/11582 ,  G11C11/4023 ,  H01L27/10805 ,  H01L27/10844 ,  H01L28/00

Abstract: Embodiments of the present disclosure describe an integrated circuit that may include a first transistor on a first side of a semiconductor substrate and a second transistor on a second side of the semiconductor substrate, wherein the second side is opposite and parallel to the first side. In embodiments, the integrated circuit may further include a first capacitor positioned on the first side of the semiconductor substrate and coupled to the first transistor to form a first memory cell, and a second capacitor positioned on the second side of the semiconductor substrate and coupled to the second transistor to form a second memory cell.

公开(公告)号：US20180226492A1

公开(公告)日：2018-08-09

申请号：US15748842

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Patrick MORROW ,  Paul B. FISCHER ,  Aaron D. LILAK ,  Stephen M. CEA

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642

Abstract: Embodiments of the invention include vertically oriented long channel transistors and methods of forming such transistors. In one embodiment, a method of forming such a transistor may include forming a fin on a semiconductor substrate. Embodiments may also include forming a spacer over an upper portion of the fin and a lower portion of the fin not covered by the spacer may be exposed. Embodiments may also include forming a gate dielectric layer over the exposed portion of the fin. A gate electrode may then be deposited, according to an embodiment. Embodiments may include exposing a top portion of the fin and forming a first source/drain (S/D) region in the top portion of the fin. The second S/D region may be formed by removing the semiconductor substrate to expose a bottom portion of the fin and forming the second S/D region in the bottom portion of the fin.

公开(公告)号：US20180204932A1

公开(公告)日：2018-07-19

申请号：US15570965

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Partick MORROW ,  Ranjith KUMAR ,  Cory E. WEBER ,  Seiyon KIM ,  Stephen M. CEA ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L27/108

CPC classification number: H01L29/66795 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/10826 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/78 ,  H01L29/785

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US20180151702A1

公开(公告)日：2018-05-31

申请号：US15576251

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Gopinath BHIMARASETTI ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Anand S. MURTHY ,  Rishabh MEHANDRU

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/02546 ,  H01L23/49827 ,  H01L23/49838 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: A method including forming a non-planar conducting channel of a multi-gate device on a substrate, the channel including a height dimension defined from a base at a surface of the substrate; modifying less than an entire portion of the channel; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. An apparatus including a non-planar multi-gate device on a substrate including a channel including a height dimension defining a conducting portion and an oxidized portion and a gate stack disposed on the channel, the gate stack including a dielectric material and a gate electrode.

公开(公告)号：US20250151363A1

公开(公告)日：2025-05-08

申请号：US19012094

申请日：2025-01-07

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Pratik A. PATEL ,  Ralph T. TROEGER ,  Szuya S. LIAO

IPC: H10D64/23 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/321 ,  H10D30/01 ,  H10D62/13 ,  H10D64/01 ,  H10D64/62 ,  H10D64/66

Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

公开(公告)号：US20240008253A1

公开(公告)日：2024-01-04

申请号：US17855545

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES ,  Cory WEBER ,  Rishabh MEHANDRU ,  Sagar SUTHRAM ,  Pushkar RANADE

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10826

Abstract: Structures having memory access transistors with backside contacts are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a fin-based transistor, and a capacitor structure above the fin-based transistor of the device layer. A backside structure is below the front-side structure. The backside structure includes a conductive contact electrically connected to the fin-based transistor of the device layer.

公开(公告)号：US20240006531A1

公开(公告)日：2024-01-04

申请号：US17855573

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Rishabh MEHANDRU ,  Sagar SUTHRAM ,  Cory WEBER ,  Tahir GHANI ,  Anand S. MURTHY ,  Pushkar RANADE ,  Wilfred GOMES

IPC: H01L29/78 ,  H01L27/13 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L27/13 ,  H01L27/124 ,  H01L29/66666

Abstract: Structures having vertical transistors are described. In an example, an integrated circuit structure includes a channel structure on a drain contact layer, the channel structure having an opening extending there through. A gate dielectric layer is on a bottom and along sides of the opening, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. A source contact layer is on sides of a portion of the gate dielectric layer extending above the channel structure.

公开(公告)号：US20240006317A1

公开(公告)日：2024-01-04

申请号：US17855586

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Cory WEBER ,  Rishabh MEHANDRU ,  Wilfred GOMES ,  Sagar SUTHRAM

IPC: H01L23/528 ,  H01L23/535 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L23/5286 ,  H01L23/535 ,  H01L29/785 ,  H01L21/76898 ,  H01L27/0924 ,  H01L21/823871

Abstract: Structures having vertical keeper or power gate for backside power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of fin-based transistors, and a plurality of metallization layers above the fin-based transistors of the device layer. A backside structure is below the fin-based transistors of the device layer. The backside structure includes a ground metal line. One or more vertical gate all-around transistors is between the fin-based transistors of the device layer and the ground metal line of the backside structure.

公开(公告)号：US20240006305A1

公开(公告)日：2024-01-04

申请号：US17855017

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Anand S. MURTHY ,  Tahir GHANI ,  Rishabh MEHANDRU ,  Cory WEBER

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775

CPC classification number: H01L23/5226 ,  H01L23/5286 ,  H01L23/5329 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/775

Abstract: Structures having airgaps for backside signal routing or power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a first conductive line laterally spaced apart from a second conductive line by an air gap.

公开(公告)号：US20230317808A1

公开(公告)日：2023-10-05

申请号：US17700002

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Cory WEBER ,  Clifford ONG ,  Sukru YEMENICIOGLU ,  Tahir GHANI ,  Brian GREENE

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/78696

Abstract: Embodiments of the present disclosure include integrated circuit structures having differentiated channel sizing, and methods of fabricating integrated circuit structures having differentiated channel sizing. In an example, a structure includes a memory region having a first vertical stack of horizontal nanowires having a first number of nanowires. The integrated circuit structure also includes a logic region having a second vertical stack of horizontal nanowires spaced apart from the first vertical stack of horizontal nanowires. The second vertical stack of horizontal nanowires has a second number of nanowires less than the first number of nanowires.