公开(公告)号：US07026238B2

公开(公告)日：2006-04-11

申请号：US10052681

申请日：2002-01-17

申请人： Ming Xi ,  Paul Frederick Smith ,  Ling Chen ,  Michael X. Yang ,  Mei Chang ,  Fusen Chen ,  Christophe Marcadal ,  Jenny C. Lin

发明人： Ming Xi ,  Paul Frederick Smith ,  Ling Chen ,  Michael X. Yang ,  Mei Chang ,  Fusen Chen ,  Christophe Marcadal ,  Jenny C. Lin

IPC分类号： H01L21/4763

CPC分类号： H01L21/76804 ,  C25D5/02 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention provide a process sequence and related hardware for filling a patterned feature on a substrate with a metal, such as copper. The sequence comprises first forming a reliable barrier layer in the patterned feature to prevent diffusion of the metal into the dielectric layer through which the patterned feature is formed. One sequence comprises forming a generally conformal barrier layer over a patterned dielectric, etching the barrier layer at the bottom of the patterned feature, depositing a second barrier layer, and then filling the patterned feature with a metal, such as copper.

公开(公告)号：US06913680B1

公开(公告)日：2005-07-05

申请号：US09614407

申请日：2000-07-12

申请人： Bo Zheng ,  Hougong Wang ,  Girish Dixit ,  Fusen Chen

发明人： Bo Zheng ,  Hougong Wang ,  Girish Dixit ,  Fusen Chen

IPC分类号： C25D5/18 ,  C25D7/12 ,  C25D13/22 ,  C25D21/12 ,  H01L21/288 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768

CPC分类号： H01L21/76877 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D21/12 ,  H01L21/2885

摘要： A method and associated apparatus includes depositing metal on a plating surface of an object immersed in an electrolyte solution prior to bulk deposition on the plating surface. In one aspect, the method further includes applying a voltage between an anode and the plating surface to enhance the concentration of metal ions in the electrolyte solution that is contained in a feature on the plating surface prior to the bulk deposition on the plating surface.

摘要翻译： 一种方法和相关设备包括在沉积在电镀表面上之前，在浸在电解质溶液中的物体的电镀表面上沉积金属。 一方面，该方法还包括在阳极和电镀表面之间施加电压，以增强在电镀表面上的主体沉积之前在电镀表面上的特征中包含的电解质溶液中的金属离子的浓度。

公开(公告)号：US06679981B1

公开(公告)日：2004-01-20

申请号：US09569736

申请日：2000-05-11

申请人： Shaoher X. Pan ,  Hiroji Hanawa ,  John C. Forster ,  Fusen Chen

发明人： Shaoher X. Pan ,  Hiroji Hanawa ,  John C. Forster ,  Fusen Chen

IPC分类号： C23C1434

CPC分类号： H01J37/321 ,  H01J37/3408

摘要： A plasma reaction chamber, particularly a DC magnetron sputter reactor, in which the plasma density and the ionization fraction of the plasma is increased by a plasma inductive loop passing through the processing space. A tube has its two ends connected to the vacuum chamber on confronting sides of the processing space. An RF coil powered by an RF power supply is positioned adjacent to the tube outside of the chamber and aligned to produce an RF magnetic field around the toroidal circumference of the tube such that an electric field is induced along the tube axis. Thereby, a plasma is generated in the tube in a loop circling through the processing space.

摘要翻译： 一种等离子体反应室，特别是直流磁控溅射反应器，其中等离子体的等离子体密度和离子化分数由通过处理空间的等离子体感应回路增加。 管子的两端连接到处理空间相对侧的真空室。 由RF电源供电的RF线圈定位成与腔室外部的管相邻，并对齐以在管的环形圆周周围产生RF磁场，使得沿着管轴引起电场。 由此，在管中产生等离子体，环路通过处理空间。

公开(公告)号：US06383915B1

公开(公告)日：2002-05-07

申请号：US09244280

申请日：1999-02-03

申请人： Jingang Su ,  Gongda Yao ,  Zhang Xu ,  Fusen Chen

发明人： Jingang Su ,  Gongda Yao ,  Zhang Xu ,  Fusen Chen

IPC分类号： H01L214763

CPC分类号： H01L21/76846 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877

摘要： We have discovered particular wetting layer or wetting/barrier layer structures which enable depositing of overlying aluminum interconnect layers having texturing sufficient to provide a Rocking Curve FWHM angle &thgr; of about 1° or less. The aluminum interconnect layer exhibiting a Rocking Curve FWHM angle &thgr; of about 1° or less exhibits excellent electromigration properties. In addition when the aluminum layer is subsequently pattern etched, the sidewalls of the etched aluminum pattern exhibit a surprising reduction in pitting compared with pattern etched aluminum layers exhibiting higher Rocking Curve FWHM angles.

摘要翻译： 我们已经发现了特定的润湿层或润湿/阻挡层结构，其能够沉积具有足以提供约1°或更小的摇摆曲线FWHM角度θ的<111>纹理的上覆铝互连层。 表现出约1°或更小的摇摆曲线FWHM角度θ的铝互连层表现出优异的电迁移性能。 此外，当铝层随后进行图案蚀刻时，与显示较高的摇摆曲线FWHM角度的图案蚀刻的铝层相比，蚀刻的铝图案的侧壁显示出令人惊讶的点蚀减少。

公开(公告)号：US06355560B1

公开(公告)日：2002-03-12

申请号：US09209434

申请日：1998-12-10

申请人： Roderick Craig Mosely ,  Hong Zhang ,  Fusen Chen ,  Ted Guo

发明人： Roderick Craig Mosely ,  Hong Zhang ,  Fusen Chen ,  Ted Guo

IPC分类号： H01L214763

CPC分类号： H01L21/76876 ,  C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

摘要： The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.

摘要翻译： 本发明一般涉及在衬底上提供均匀的台阶覆盖和金属层的平坦化以在半微米应用中形成连续的无空隙接触或通孔的改进方法。 在本发明的一个方面中，将耐火层沉积在具有高比例接触或在其上形成的通孔的基底上。 然后在低温下将CVD金属层沉积到耐火层上，以提供用于PVD金属的保形润湿层。 接下来，在低于金属的熔点温度的温度下，将PVD金属沉积在预先形成的CVD金属层上。 所得到的CVD / PVD金属层基本上无空隙。 金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，就会发生通孔和触点的金属化，而不会在其上形成氧化物层 CVD Al层。

公开(公告)号：US5319245A

公开(公告)日：1994-06-07

申请号：US981908

申请日：1992-11-23

申请人： Fusen Chen ,  Fu-Tai Liou ,  Girish Dixit

发明人： Fusen Chen ,  Fu-Tai Liou ,  Girish Dixit

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L23/48 ,  H01L29/46 ,  H01L29/62 ,  H01L29/64

CPC分类号： H01L23/53257 ,  H01L21/76889 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S257/915

摘要： A method for fabrication of local interconnects in an integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to the disclosed embodiment, a first and a second conductive structure are formed over the integrated circuit. An insulating layer is formed over the integrated. A first photoresist layer is formed over the insulating layer, patterned and developed. The insulating layer is etched to expose selected regions of the first and second conductive structures. A refractory metal layer is formed over the integrated circuit. A barrier layer is formed over the refractory metal layer, and optionally a refractory metal silicide layer is formed over the barrier layer. A second photoresist layer is formed over the barrier layer, patterned and developed. The refractory metal layer and barrier layer, and the refractory metal silicide layer if formed, are etched to define a conductive interconnect between the exposed selected regions of the first and second conductive structures.

摘要翻译： 公开了一种用于制造集成电路中的局部互连的方法，以及根据该集成电路形成的集成电路。 根据所公开的实施例，在集成电路上形成第一和第二导电结构。 在整合上形成绝缘层。 第一光致抗蚀剂层形成在绝缘层上，被图案化和显影。 蚀刻绝缘层以暴露第一和第二导电结构的选定区域。 在集成电路上形成难熔金属层。 在耐火金属层之上形成阻挡层，并且可选地在阻挡层上形成难熔金属硅化物层。 第二光致抗蚀剂层形成在阻挡层上，被图案化和显影。 难熔金属层和阻挡层以及如果形成的难熔金属硅化物层被蚀刻以在第一和第二导电结构的暴露的选定区域之间限定导电互连。

公开(公告)号：US4933304A

公开(公告)日：1990-06-12

申请号：US266796

申请日：1988-11-03

申请人： Fusen Chen ,  Yih-Shung Lin ,  Fu-Tai Liou

发明人： Fusen Chen ,  Yih-Shung Lin ,  Fu-Tai Liou

IPC分类号： H01L21/302 ,  H01L21/027 ,  H01L21/30 ,  H01L21/3065 ,  H01L21/321 ,  H01L21/3213

CPC分类号： H01L21/0276 ,  H01L21/321 ,  Y10S148/138 ,  Y10S148/158 ,  Y10S438/952

摘要： The method for producing the surface reflectance of the metal layer during semiconductor processing includes the step of roughening the surface of a metal layer prior to forming the photoresist thereon. The roughened surface reduces reflections that can cause metal notching effects. The step of roughening the surface includes depositing a layer (34) of aluminum which is substantially thinner than the thickness of the primary metal layer by a sputtering process.

公开(公告)号：US6066358A

公开(公告)日：2000-05-23

申请号：US611108

申请日：1996-03-05

申请人： Ted Guo ,  Liang Chen ,  Fusen Chen ,  Roderick C. Mosely

发明人： Ted Guo ,  Liang Chen ,  Fusen Chen ,  Roderick C. Mosely

IPC分类号： H01L21/285 ,  C23C14/56 ,  C23C16/54 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/677 ,  H01L21/768 ,  B05D5/12 ,  C23C14/04 ,  C23C16/04 ,  C23C16/06

CPC分类号： H01L21/76876 ,  C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

摘要： The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of conducting layers to form continuous, void-free interconnects in sub-half micron, high aspect ratio aperture width applications and highly oriented conducting layers. In one aspect of the invention, a dielectric layer is formed over a conducting or semiconducting layer and etched to form an aperture exposing the underlying conducting or semiconducting layer on the aperture floor. An ultra-thin nucleation layer is then deposited by physical vapor deposition onto the field of the dielectric layer. A CVD metal layer is then deposited onto the structure to achieve selective deposition on the floor of the aperture, while preferably also forming a highly oriented blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the apertures to form vias and contacts occurs without the formation of oxides between the layers.

摘要翻译： 本发明一般涉及一种改进的装置和方法，用于在衬底上提供均匀的台阶覆盖和导电层的平坦化，以形成半微米，高纵横比孔径宽度应用和高度取向导电层的连续的无空隙互连。 在本发明的一个方面，电介质层形成在导电或半导体层之上，并被蚀刻以形成露出孔底板上下面的导电或半导体层的孔。 然后通过物理气相沉积将超薄成核层沉积到介电层的场上。 然后将CVD金属层沉积到结构上以实现孔的地板上的选择性沉积，同时优选地还在场上形成高度取向的覆盖层。 本装置和工艺减少了制造基本上无空隙和平坦化的CVD金属互连和层所需的步骤数量。 金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，孔的金属化形成通孔和接触，而不会在两者之间形成氧化物之间 层。