公开(公告)号：US6090963A

公开(公告)日：2000-07-18

申请号：US281722

申请日：1999-03-30

申请人： Wei-Wei Zhuang ,  Tue Nguyen ,  Robert Barrowcliff ,  David Russell Evans ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Tue Nguyen ,  Robert Barrowcliff ,  David Russell Evans ,  Sheng Teng Hsu

IPC分类号： C07C11/02 ,  C07C49/92 ,  C07F1/08 ,  C23C16/18

CPC分类号： C23C16/18

摘要： A metal(hfac), alkene ligand precursor has been provided. The alkene ligand includes double bonded carbon atoms, with first and second bonds to the first carbon atom, and third and fourth bonds to the second carbon atom. The first, second, third, and fourth bonds are selected from a the group consisting of H, C.sub.1 to C.sub.8 alkyl, C.sub.1 to C.sub.8 haloalkyl, and C.sub.1 to C.sub.8 alkoxyl. As a general class, these precursors are capable of high metal deposition rates and high volatility, despite being stable in the liquid phase at low temperatures. Copper deposited with this precursor has low resistivity and high adhesive characteristics. A synthesis method has been provided which produces a high yield of the above-described alkene ligand class of metal precursors.

摘要翻译： 已经提供了金属（hfac），烯烃配体前体。 烯属配体包括双键键合的碳原子，与第一个碳原子具有第一个和第二个键，第三个和第四个键连接到第二个碳原子。 第一，第二，第三和第四键选自H，C 1至C 8烷基，C 1至C 8卤代烷基和C 1至C 8烷氧基。 作为一般类别，尽管在低温下在液相中稳定，但这些前体能够具有高的金属沉积速率和高挥发性。 沉积有该前体的铜具有低电阻率和高粘合特性。 已经提供了产生上述烯属配体类金属前体的高产率的合成方法。

公开(公告)号：US6048738A

公开(公告)日：2000-04-11

申请号：US870375

申请日：1997-06-06

申请人： Sheng Teng Hsu ,  Jong Jan Lee

发明人： Sheng Teng Hsu ,  Jong Jan Lee

IPC分类号： G11C11/22 ,  H01L21/28 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/115 ,  H01L29/78 ,  H01G7/06

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L21/28291 ,  H01L21/84 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/78391 ,  G11C11/223

摘要： A method of forming a semiconductor memory device on a silicon substrate includes implanting doping impurities of a first type in the silicon substrate to form a conductive channel of a first type for use as a gate junction region, forming a MOS capacitor on the conductive channel of the first type, depositing an FEM capacitor over the MOS capacitor, thereby forming a stacked gate unit, implanting doping impurities of a second type in the silicon substrate on either side of the gate junction region to form a conductive channel of a second type for use as a source junction region and a drain junction region, and depositing an insulating structure about the FEM gate unit. A ferroelectric memory (FEM) cell constructed according to the invention includes a silicon substrate, a gate region located in said substrate, a source junction region and a drain junction region located on either side of said gate region, a MOS capacitor, a FEM capacitor, wherein said FEM capacitor is stacked on and overlays at least a portion of said MOS capacitor, thereby forming, with said MOS capacitor, a stacked gate unit.

摘要翻译： 在硅衬底上形成半导体存储器件的方法包括在硅衬底中注入第一类型的掺杂杂质以形成用作栅极结区域的第一类型的导电沟道，在导电沟道上形成MOS电容器 第一类型，在MOS电容器上沉积FEM电容器，从而形成堆叠栅极单元，在栅极结区域的任一侧上在硅衬底中注入第二类型的掺杂杂质以形成第二类型的导电沟道用于 作为源极结区域和漏极结区域，以及围绕FEM栅极单元沉积绝缘结构。 根据本发明构造的铁电存储器（FEM）单元包括硅衬底，位于所述衬底中的栅极区，位于所述栅极区两侧的源极结区域和漏极结区域，MOS电容器，FEM电容器 ，其中所述FEM电容器堆叠在所述MOS电容器的至少一部分上并覆盖所述MOS电容器，从而与所述MOS电容器形成堆叠栅极单元。

公开(公告)号：US5904565A

公开(公告)日：1999-05-18

申请号：US896114

申请日：1997-07-17

申请人： Tue Nguyen ,  Sheng Teng Hsu

发明人： Tue Nguyen ,  Sheng Teng Hsu

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/522 ,  H01L21/44

CPC分类号： H01L21/76844 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76865 ,  H01L23/5226 ,  H01L21/28568 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A method of forming a direct, copper-to-copper, connection between levels in an IC is disclosed. A via interconnection is formed by isotropically depositing a barrier material in a via through an insulator to a lower copper level, and then anisotropically etching the via to remove the barrier material covering the lower copper level. The anisotropic etch leaves the barrier material lining the via through the insulator. The subsequently deposited upper metal level then directly contacts the lower copper level when the via is filled. A dual damascene interconnection is formed by etching an interconnection trench in an insulator and anisotropically depositing a non-conductive barrier material in the trench bottom. Then a via is formed from the trench interconnect to a lower copper level. As above, a conductive barrier material is isotropically deposited in the trench/via structure, and anisotropically etched to remove the barrier material covering the lower copper level. The insulating barrier material, lining the trench and via, remains. An IC via interconnection structure and a dual damascene interconnection structure, made in accordance with the above described methods, are also provided.

摘要翻译： 公开了一种在IC中形成直接铜铜铜连接电平的方法。 通过互连形成通过绝缘体将通孔绝缘体上的阻挡材料各向同性地沉积到较低的铜电平，然后各向异性地蚀刻通孔以除去覆盖较低铜层的阻挡材料。 各向异性蚀刻离开通过绝缘体衬套通孔的阻挡材料。 随后沉积的上层金属层，当通孔填充时，直接接触下铜层。 通过蚀刻绝缘体中的互连沟槽并且在沟槽底部中各向异性地沉积非导电阻挡材料来形成双镶嵌互连。 然后，通孔从沟槽互连形成为较低的铜层。 如上所述，导电阻挡材料在沟槽/通孔结构中各向同性地沉积，并进行各向异性蚀刻以去除覆盖较低铜层的阻挡材料。 绝缘阻隔材料，衬在沟槽和通孔，仍然存在。 还提供了根据上述方法制造的通过互连结构和双镶嵌互连结构的IC。

公开(公告)号：US5891782A

公开(公告)日：1999-04-06

申请号：US918678

申请日：1997-08-21

申请人： Sheng Teng Hsu ,  Jong Jan Lee

发明人： Sheng Teng Hsu ,  Jong Jan Lee

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/786 ,  H01L21/8234

CPC分类号： H01L29/78624 ,  H01L29/66772 ,  H01L29/78696

摘要： A method of forming a MOS transistor without a lightly doped drain (LDD) region between the channel region and drain is provided. The channel region is formed from a tilted ion implantation after the deposition of the gate oxide layer. The tilted implantation forms a relatively short channel length, with respect to the length of the gate electrode. The position of the channel is offset, and directly adjoins the source. The non-channel area under the gate, adjacent the drain, replaces the LDD region between the channel and the drain. This drain extension acts to more evenly distribute electric fields so that large breakdown voltages are possible. The small channel length, and eliminated LDD region adjacent the source, act to reduce resistance between the source and drain. In this manner, larger I.sub.d currents and faster switching speeds are obtained. A MOS transistor having a short, offset channel and drain extension is also provided.

摘要翻译： 提供了一种形成在沟道区和漏极之间没有轻掺杂漏极（LDD）区的MOS晶体管的方法。 沟道区域是在淀积栅极氧化物层之后由倾斜的离子注入形成的。 相对于栅电极的长度，倾斜注入形成相对短的沟道长度。 通道的位置偏移，并直接与源相邻。 在漏极附近的栅极下方的非沟道区域替代通道和漏极之间的LDD区域。 这种漏极扩展用于更均匀地分布电场，使得可以实现大的击穿电压。 较小的通道长度和消除与源极相邻的LDD区域起到降低源极和漏极之间的电阻的作用。 以这种方式，获得更大的Id电流和更快的开关速度。 还提供了具有短的偏置沟道和漏极延伸的MOS晶体管。

公开(公告)号：US07968419B2

公开(公告)日：2011-06-28

申请号：US12234663

申请日：2008-09-21

申请人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans

发明人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans

IPC分类号： H01L21/20

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.

摘要翻译： 提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。 该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。 响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。 通常，响应于Si厚度的增加，阈值和击穿电压都增加。 关于开/关电流比，存在最佳厚度。 该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。

公开(公告)号：US07727897B2

公开(公告)日：2010-06-01

申请号：US11215519

申请日：2005-08-30

申请人： Bruce D. Ulrich ,  Lisa H. Stecker ,  Fengyan Zhang ,  Sheng Teng Hsu

发明人： Bruce D. Ulrich ,  Lisa H. Stecker ,  Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： H01L21/302

CPC分类号： H01L28/55 ,  H01L21/31122

摘要： A method of etching a top electrode/ferroelectric stack using an etch stop layer includes forming a first layer of a first dielectric material on a substrate; forming a bottom electrode in the first layer of a first dielectric material; depositing an etch stop layer on the first layer of the first dielectric material and the bottom electrode, including forming a hole therein; depositing a layer of ferroelectric material and depositing top electrode material on the ferroelectric material to form a top electrode/ferroelectric stack; stack etching the top electrode and ferroelectric material; depositing a layer of a second dielectric material encapsulating the top electrode and ferroelectric material; etching the layer of the second dielectric material to form a sidewall about the top electrode and ferroelectric material; and depositing a second and third layers of the first dielectric material.

摘要翻译： 使用蚀刻停止层蚀刻顶部电极/铁电体堆叠的方法包括在衬底上形成第一电介质材料的第一层; 在第一介电材料的第一层中形成底电极; 在所述第一电介质材料和所述底电极的所述第一层上沉积蚀刻停止层，包括在其中形成孔; 沉积一层铁电材料层并在铁电材料上沉积顶部电极材料以形成顶部电极/铁电堆叠; 堆叠蚀刻顶部电极和铁电材料; 沉积封装上电极和铁电材料的第二电介质材料层; 蚀刻第二介电材料的层以形成围绕顶电极和铁电材料的侧壁; 以及沉积所述第一介电材料的第二和第三层。

公开(公告)号：US07675056B2

公开(公告)日：2010-03-09

申请号：US11891574

申请日：2007-08-10

申请人： Jong-Jan Lee ,  Sheng Teng Hsu ,  Jer-Shen Maa ,  Douglas J. Tweet

发明人： Jong-Jan Lee ,  Sheng Teng Hsu ,  Jer-Shen Maa ,  Douglas J. Tweet

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/062 ,  H01L31/113 ,  H01L31/0232

CPC分类号： H01L31/1136 ,  H01L31/028 ,  H01L31/1808 ,  Y02E10/547

摘要： A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.

摘要翻译： 提出了一种浮体锗（Ge）光电晶体管及其制造工艺。 该方法包括：提供硅（Si）衬底; 选择性地形成覆盖Si衬底的绝缘体层; 使用液相外延（LPE）工艺形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成覆盖所述沟道区的栅极电介质，栅电极和栅极间隔; 并且在Ge层中形成源/漏区。 LPE工艺包括用具有大于第一温度的熔化温度的材料包封Ge，并且使用低于第一温度的温度来熔化Ge。 LPE工艺包括：形成覆盖沉积Ge的介电层; 融化Ge; 并且响应于冷却Ge，将外延生长前沿从下面的Si衬底表面横向传播到Ge中。

公开(公告)号：US07608874B2

公开(公告)日：2009-10-27

申请号：US11657152

申请日：2007-01-24

申请人： Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L31/062 ,  H01L31/113

CPC分类号： H01L27/14647 ,  H01L27/1463 ,  H01L27/14689

摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, together with an associated fabrication method. The method provides a bulk silicon (Si) substrate. A plurality of color imager cells are formed, either in the Si substrate, or in a single epitaxial Si layer formed over the substrate. Each color imager cell includes a photodiode set with a first, second, and third photodiode formed as a stacked multi-junction structure. A U-shaped (in cross-section) well liner, fully isolates the photodiode set from adjacent photodiode sets in the array. For example, each photodiode is formed from a p doped Si layer physically interfaced to a first wall. A well bottom physically interfaces to the first wall, and the p doped Si layer of the third, bottom-most, photodiode is part of the well bottom. Then, the photodiode sets may be formed from an n/p/n/p/n/p or n/p/p−/p/p−/p layered structure.

摘要翻译： 提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，以及相关的制造方法。 该方法提供体硅（Si）衬底。 在Si衬底中或在衬底上形成的单个外延Si层中形成多个彩色成像器单元。 每个彩色成像器单元包括具有形成为堆叠多结结构的第一，第二和第三光电二极管。 U形（横截面）井衬管，将阵列中的光电二极管组与相邻的光电二极管组完全隔离。 例如，每个光电二极管由物理上与第一壁物理连接的p掺杂Si层形成。 阱底部与第一壁物理接口，第三，最底部的光电二极管的p掺杂Si层是阱底部的一部分。 然后，光电二极管组可以由n / p / n / p / n / p或n / p / p / p / p / p层叠结构形成。

公开(公告)号：US07608514B2

公开(公告)日：2009-10-27

申请号：US11900999

申请日：2007-09-15

申请人： Sheng Teng Hsu ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Tingkai Li

IPC分类号： H01L21/336

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over the memory resistor material. An MSM bottom electrode overlies the memory resistor top electrode, a semiconductor layer overlies the MSM bottom electrode, and an MSM top electrode overlies the semiconductor layer. The MSM bottom electrode can be a material such as Pt, Ir, Au, Ag, TiN, or Ti. The MSM top electrode can be a material such as Pt, Ir, Au, TiN, Ti, or Al. The semiconductor layer can be amorphous Si, ZnO2, or InO2.

摘要翻译： 提供金属/半导体/金属（MSM）二进制开关存储器件和制造工艺。 该器件包括存储器电阻器底部电极，存储器电阻器底部电极上方的存储器电阻器材料，以及存储器电阻器材料上的存储器电阻器顶部电极。 MSM底部电极覆盖存储电阻器顶部电极，半导体层覆盖在MSM底部电极上，并且MSM顶部电极覆盖半导体层。 MSM底部电极可以是诸如Pt，Ir，Au，Ag，TiN或Ti的材料。 MSM顶部电极可以是诸如Pt，Ir，Au，TiN，Ti或Al的材料。 半导体层可以是非晶Si，ZnO 2或InO 2。

公开(公告)号：US07585788B2

公开(公告)日：2009-09-08

申请号：US11224549

申请日：2005-09-12

申请人： Wei-Wei Zhuang ,  Yoshi Ono ,  Sheng Teng Hsu ,  Tingkai Li

发明人： Wei-Wei Zhuang ,  Yoshi Ono ,  Sheng Teng Hsu ,  Tingkai Li

IPC分类号： H01L21/31

CPC分类号： H01L21/02156 ,  H01L21/02282 ,  H01L21/316

摘要： A method is provided for forming a rare earth element-doped silicon oxide (SiO2) precursor with nanocrystalline (nc) Si particles. In one aspect the method comprises: mixing Si particles into a first organic solvent, forming a first solution with a first boiling point; filtering the first solution to remove large Si particles; mixing a second organic solvent having a second boiling point, higher than the first boiling point, to the filtered first solution; and, fractionally distilling, forming a second solution of nc Si particles. The Si particles are formed by immersing a Si wafer into a third solution including hydrofluoric (HF) acid and alcohol, applying an electric bias, and forming a porous Si layer overlying the Si wafer. Then, the Si particles are mixed into the organic solvent by depositing the Si wafer into the first organic solvent, and ultrasonically removing the porous Si layer from the Si wafer.

摘要翻译： 提供了一种用于形成具有纳米晶体（nc）Si颗粒的稀土元素掺杂的氧化硅（SiO 2）前体的方法。 一方面，该方法包括：将Si颗粒混合到第一有机溶剂中，形成具有第一沸点的第一溶液; 过滤第一溶液以除去大的Si颗粒; 将具有高于第一沸​​点的第二沸点的第二有机溶剂与过滤的第一溶液混合; 并分馏，形成nc Si颗粒的第二溶液。 通过将Si晶片浸入包括氢氟酸（HF）酸和醇的第三溶液中，施加电偏压并形成覆盖Si晶片的多孔Si层，形成Si颗粒。 然后，通过将Si晶片沉积到第一有机溶剂中，将Si颗粒混入有机溶剂中，并从Si晶片超声波除去多孔Si层。