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277 条记录 (耗时 0.052 秒)

    Method for manufacturing semiconductor device
    63.
    发明授权
    Method for manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09178071B2

    公开(公告)日：2015-11-03

    申请号：US13225703

    申请日：2011-09-06

    申请人： Hidekazu Miyairi ,  Koji Dairiki ,  Shunpei Yamazaki ,  Ryo Arasawa

    发明人： Hidekazu Miyairi ,  Koji Dairiki ,  Shunpei Yamazaki ,  Ryo Arasawa

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/66

    CPC分类号： H01L29/78678 ,  H01L29/66765 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78669 ,  H01L29/78696

    摘要： Provided is a method for manufacturing a semiconductor device with fewer masks and in a simple process. A gate electrode is formed. A gate insulating film, a semiconductor film, an impurity semiconductor film, and a conductive film are stacked in this order, covering the gate electrode. A source electrode and a drain electrode are formed by processing the conductive film. A source region, a drain region, and a semiconductor layer, an upper part of a portion of which does not overlap with the source region and the drain region is removed, are formed by processing the upper part of the semiconductor film, while the impurity semiconductor film is divided. A passivation film over the gate insulating film, the semiconductor layer, the source region, the drain region, the source electrode, and the drain electrode are formed. An etching mask is formed over the passivation film. At least the passivation film and the semiconductor layer are processed to have an island shape while an opening reaching the source electrode or the drain electrode is formed, with the use of the etching mask. The etching mask is removed. A pixel electrode is formed over the gate insulating film and the passivation film.

    摘要翻译： 提供一种用于制造具有较少掩模的半导体器件的方法，并且在简单的过程中。 形成栅电极。 依次层叠栅绝缘膜，半导体膜，杂质半导体膜和导电膜，覆盖栅电极。 通过处理导电膜形成源电极和漏电极。 通过处理半导体膜的上部，形成源区域，漏极区域和半导体层，其部分的上部不与源极区域和漏极区域重叠，而杂质 半导体薄膜被划分。 形成栅极绝缘膜，半导体层，源极区域，漏极区域，源极电极和漏极电极之后的钝化膜。 在钝化膜上形成蚀刻掩模。 通过使用蚀刻掩模，至少钝化膜和半导体层被加工成具有岛状，同时形成到达源电极或漏电极的开口。 去除蚀刻掩模。 在栅极绝缘膜和钝化膜上形成像素电极。

    Display device
    65.
    发明授权
    Display device 有权
    显示设备

    公开(公告)号：US09048147B2

    公开(公告)日：2015-06-02

    申请号：US13613811

    申请日：2012-09-13

    申请人： Shunpei Yamazaki ,  Takeshi Osada ,  Hidekazu Miyairi ,  Yasuhiro Jinbo

    发明人： Shunpei Yamazaki ,  Takeshi Osada ,  Hidekazu Miyairi ,  Yasuhiro Jinbo

    IPC分类号： G09G3/36 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

    CPC分类号： G02F1/1368 ,  G02F1/133345 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/1365 ,  H01L27/1214 ,  H01L27/1229 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/04 ,  H01L29/78648 ,  Y10T428/24331

    摘要： A display device of which frame can be narrowed and of which display characteristics are excellent is provided. In a display device including a switch portion or a buffer portion, a logic circuit portion, and a pixel portion, the pixel portion includes a first inverted staggered TFT and a pixel electrode which is connected to a wiring of the first inverted staggered TFT, the switch portion or the buffer portion includes a second inverted staggered TFT in which a first insulating layer, a semiconductor layer, and a second insulating layer are interposed between a first gate electrode and a second gate electrode, the logic circuit portion includes an inverter circuit including a third inverted staggered thin film transistor and a fourth inverted staggered thin film transistor, and the first to the fourth inverted staggered thin film transistors have the same polarity. The inverter circuit may be an EDMOS circuit.

    摘要翻译： 提供了一种可以缩小框架并且显示特性优异的显示装置。 在包括开关部分或缓冲部分，逻辑电路部分和像素部分的显示装置中，像素部分包括连接到第一反交错TFT的布线的第一反交错TFT和像素电极， 开关部分或缓冲部分包括其中第一绝缘层，半导体层和第二绝缘层插入在第一栅电极和第二栅电极之间的第二反交错TFT，所述逻辑电路部分包括逆变器电路，包括 第三反交错薄膜晶体管和第四反交错薄膜晶体管，并且第一至第四反交错薄膜晶体管具有相同的极性。 逆变器电路可以是EDMOS电路。

    Semiconductor device comprising an oxide semiconductor layer
    66.
    发明授权
    Semiconductor device comprising an oxide semiconductor layer 有权
    半导体器件包括氧化物半导体层

    公开(公告)号：US09029851B2

    公开(公告)日：2015-05-12

    申请号：US13302222

    申请日：2011-11-22

    申请人： Hidekazu Miyairi ,  Takeshi Osada ,  Shunpei Yamazaki

    发明人： Hidekazu Miyairi ,  Takeshi Osada ,  Shunpei Yamazaki

    IPC分类号： H01L27/088 ,  H01L29/786 ,  H01L27/12

    CPC分类号： H01L29/7869 ,  H01L21/02565 ,  H01L21/47635 ,  H01L21/477 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78648

    摘要： As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

    摘要翻译： 作为显示装置具有更高的清晰度，像素数，栅极线和信号线的数量增加。 当栅极线和信号线的数量增加时，由于难以通过接合等安装包括用于驱动栅极和信号线的驱动电路的IC芯片，所以制造成本更高。 用于驱动像素部分的像素部分和驱动电路设置在相同的基板上，驱动电路的至少一部分包括薄膜晶体管，该薄膜晶体管使用介于氧化物半导体上方和下方的栅电极之间的氧化物半导体。 因此，当像素部分和驱动器部分设置在相同的基板上时，可以降低制造成本。

    Semiconductor device and manufacturing method thereof
    67.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US08907348B2

    公开(公告)日：2014-12-09

    申请号：US13478490

    申请日：2012-05-23

    申请人： Hidekazu Miyairi ,  Takeshi Osada ,  Shunpei Yamazaki

    发明人： Hidekazu Miyairi ,  Takeshi Osada ,  Shunpei Yamazaki

    IPC分类号： H01L27/14 ,  H01L27/12 ,  H01L29/786 ,  H01L27/32 ,  G02F1/1362

    CPC分类号： H01L27/1225 ,  G02F1/1362 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/3262 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78606 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/7869

    摘要： As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount IC chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided on the same substrate, and at least part of the driver circuit comprises a thin film transistor including an oxide semiconductor sandwiched between gate electrodes. A channel protective layer is provided between the oxide semiconductor and a gate electrode provided over the oxide semiconductor. The pixel portion and the driver circuit are provided on the same substrate, which leads to reduction of manufacturing cost.

    摘要翻译： 由于显示装置具有更高的清晰度，因此像素数量增加，因此栅极线和信号线的数量增加。 当栅极线和信号线的数量增加时，难以通过结合等安装包括用于驱动栅极线和信号线的驱动电路的IC芯片，由此增加制造成本。 用于驱动像素部分的像素部分和驱动电路设置在同一基板上，并且驱动电路的至少一部分包括薄膜晶体管，该薄膜晶体管包括夹在栅电极之间的氧化物半导体。 在氧化物半导体和设置在氧化物半导体上的栅电极之间设置沟道保护层。 像素部分和驱动电路设置在相同的基板上，这导致制造成本的降低。

    Semiconductor device and method for manufacturing the same
    68.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08729544B2

    公开(公告)日：2014-05-20

    申请号：US13013054

    申请日：2011-01-25

    申请人： Shunpei Yamazaki ,  Hidekazu Miyairi ,  Kengo Akimoto ,  Kojiro Shiraishi

    发明人： Shunpei Yamazaki ,  Hidekazu Miyairi ,  Kengo Akimoto ,  Kojiro Shiraishi

    IPC分类号： H01L29/22 ,  H01L29/786

    CPC分类号： H01L29/66969 ,  H01L21/46 ,  H01L27/1225 ,  H01L29/7869

    摘要： It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

    摘要翻译： 本发明的目的是提供一种包括具有良好的电性能和高可靠性的薄膜晶体管的半导体器件，以及一种以高生产率制造半导体器件的方法。 在倒置交错（底栅极）薄膜晶体管中，使用含有In，Ga和Zn的氧化物半导体膜作为半导体层，并且在半导体层和源之间设置使用金属氧化物层形成的缓冲层， 漏电极层。 有意地提供金属氧化物层作为半导体层与源极和漏极电极层之间的缓冲层，从而获得欧姆接触。

    Semiconductor device
    70.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08558236B2

    公开(公告)日：2013-10-15

    申请号：US13196926

    申请日：2011-08-03

    申请人： Shunpei Yamazaki ,  Hidekazu Miyairi ,  Yasuhiro Jinbo

    发明人： Shunpei Yamazaki ,  Hidekazu Miyairi ,  Yasuhiro Jinbo

    IPC分类号： H01L29/786

    CPC分类号： H01L27/1288 ,  H01L21/67017 ,  H01L21/67207 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1244 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66765 ,  H01L29/78678 ,  H01L29/78687 ,  H01L29/78696

    摘要： An object is to reduce off-current of a thin film transistor. Another object is to improve electric characteristics of a thin film transistor. Further, it is still another object to improve image quality of a display device using the thin film transistor. An aspect of the present invention is a thin film transistor including a semiconductor film formed over a gate electrode and in an inner region of the gate electrode which does not reach an end portion of the gate electrode, with a gate insulating film interposed therebetween, a film covering at least a side surface of the semiconductor film, and a pair of wirings over the film covering the side surface of the semiconductor film; in which an impurity element serving as a donor is added to the semiconductor film.

    摘要翻译： 目的是减少薄膜晶体管的截止电流。 另一个目的是改善薄膜晶体管的电特性。 此外，还有另一个目的是提高使用薄膜晶体管的显示装置的图像质量。 本发明的一个方面是一种薄膜晶体管，它包括半导体膜，该半导体膜形成在栅电极之上，并且在栅电极的内部区域中，其不到达栅电极的端部，栅极绝缘膜介于它们之间， 至少覆盖半导体膜的侧面的膜，以及覆盖半导体膜的侧面的膜上的一对配线; 其中作为供体的杂质元素被添加到半导体膜。