公开(公告)号：US20180012660A1

公开(公告)日：2018-01-11

申请号：US15669311

申请日：2017-08-04

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/04 ,  G11C16/16 ,  G11C11/56 ,  G11C16/08 ,  H01L27/105 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  H01L27/1052 ,  H01L27/115 ,  H01L28/00

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US09754889B2

公开(公告)日：2017-09-05

申请号：US14975746

申请日：2015-12-19

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/535 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/535 ,  H01L21/743 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/5283 ,  H01L28/00 ,  H01L29/41766 ,  H01L29/4236

Abstract: An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. A conductive via extends elevationally into the material of the one terminal. The conductive via extends laterally into the material of the one terminal under the upper surface of the one terminal. Material of the one terminal is above at least some of the laterally extending conductive via. Other embodiments, including method embodiments, are disclosed.

公开(公告)号：US09741737B1

公开(公告)日：2017-08-22

申请号：US15130803

申请日：2016-04-15

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L27/1157 ,  H01L28/00

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US09728266B1

公开(公告)日：2017-08-08

申请号：US15205574

申请日：2016-07-08

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C16/16

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  H01L27/1052 ,  H01L27/115 ,  H01L28/00

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US09449978B2

公开(公告)日：2016-09-20

申请号：US14148402

申请日：2014-01-06

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Mingtao Li ,  Haitao Liu ,  Deepak Chandra Pandey ,  Mark Fischer

IPC: H01L27/108 ,  H01L27/105 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/10879 ,  H01L27/1052 ,  H01L27/10891 ,  H01L29/66613 ,  H01L29/66818 ,  H01L29/785 ,  H01L2029/7857

Abstract: A semiconductor device comprises a recessed access device that includes a first pillar, a second pillar, a channel region connecting the first and second pillars, and a gate disposed over the channel region. The channel region has a width that is narrower than widths of the first pillar and the second pillar. An array of recessed access devices comprises a plurality of pillars protruding from a substrate, and a plurality of channel regions. Each channel region has a width that is less than about 10 nm and couples neighboring pillars to form a plurality of junctionless recessed access devices. A method of forming at least one recessed access device also comprises forming pillars over a substrate, forming at least a channel region coupled with the pillars, the channel region having a relatively narrow width, and forming a gate at least partially surrounding the channel region on at least three sides.

Abstract translation: 一种半导体器件包括凹入的存取器件，其包括第一柱，第二柱，连接第一和第二柱的沟道区，以及设置在沟道区上的栅。 沟道区具有比第一柱和第二柱的宽度窄的宽度。 凹陷进入装置的阵列包括从基板突出的多个支柱和多个通道区域。 每个通道区域具有小于约10nm的宽度并且连接相邻的柱以形成多个无连接的凹入式接入设备。 一种形成至少一个凹陷进入装置的方法还包括在衬底上形成柱，形成至少与柱相连的沟道区，沟道区具有相对较窄的宽度，以及形成至少部分围绕沟道区的栅极 至少三面。

公开(公告)号：US20160155745A1

公开(公告)日：2016-06-02

申请号：US15005360

申请日：2016-01-25

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kamal M. Karda ,  Wolfgang Mueller ,  Sourabh Dhir ,  Robert Kerr ,  Sangmin Hwang ,  Haitao Liu

IPC: H01L27/108 ,  H01L29/06 ,  H01L23/528

CPC classification number: H01L27/10823 ,  H01L21/76232 ,  H01L23/528 ,  H01L27/10808 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66477 ,  H01L29/66621 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/1436 ,  H01L2924/00

Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

Abstract translation: 一组凹进的存取栅极线包括其间具有介电沟槽隔离材料的有源区域区域。 沟槽隔离材料包括延伸到有源区域区域的材料的最外表面下方的各个有源区域的相对端的电介质突起。 有源区域材料在电介质突起上是垂直的。 嵌入式栅极线分别横跨有源区域区域延伸并且在电介质沟槽隔离材料内的紧邻端到端相邻有源区域区域的端部之间延伸。 公开了其他阵列，方法也是如此。

公开(公告)号：US20160126354A1

公开(公告)日：2016-05-05

申请号：US14992966

申请日：2016-01-11

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Fawad Ahmed ,  Kamal M. Karda

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/0692 ,  H01L29/42356 ,  H01L29/66795

Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.

公开(公告)号：US20160104709A1

公开(公告)日：2016-04-14

申请号：US14511371

申请日：2014-10-10

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Sourabh Dhir ,  Rajesh N. Gupta ,  Sanh D. Tang ,  Si-Woo Lee ,  Haitao Liu

IPC: H01L27/108 ,  G11C11/407

CPC classification number: H01L27/10826 ,  G11C7/02 ,  G11C11/407 ,  G11C11/4097 ,  H01L27/10879

Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.

Abstract translation: 用于存储器件制造的方法包括在衬底上形成多个连续的翅片。 在翅片周围形成绝缘体材料。 将连续的翅片蚀刻成分段的翅片以在分段翅片之间形成暴露的区域。 在暴露区域中形成绝缘体材料，其中暴露区域中的绝缘体材料形成为高于鳍片周围的绝缘体材料。 在翅片和绝缘体材料上形成金属。 形成在暴露区域上的金属形成为比鳍片上方浅的深度。

公开(公告)号：US20150364377A1

公开(公告)日：2015-12-17

申请号：US14836257

申请日：2015-08-26

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Fawad Ahmed ,  Kamal M. Karda

IPC: H01L21/8234 ,  H01L21/306

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/0692 ,  H01L29/42356 ,  H01L29/66795

Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.

公开(公告)号：US20150243748A1

公开(公告)日：2015-08-27

申请号：US14190807

申请日：2014-02-26

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Haitao Liu ,  Sanh D. Tang ,  Wolfgang Mueller ,  Sourabh Dhir

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/7827

Abstract: A vertical access device comprises a semiconductive base comprising a first source/drain region, a semiconductive pillar extending vertically from the semiconductive base, and a gate electrode adjacent a sidewall of the semiconductive pillar. The semiconductive pillar comprises a channel region overlying the first source/drain region, and a second source/drain region overlying the channel region. An opposing sidewall of the semiconductive pillar is not adjacent the gate electrode or another gate electrode. Semiconductive device structures, methods of forming a vertical access device, and methods of forming a semiconductive structure are also described.

Abstract translation: 垂直存取装置包括半导体基底，其包括第一源极/漏极区域，从半导体基底垂直延伸的半导体柱和邻近半导体支柱的侧壁的栅电极。 半导体柱包括覆盖第一源极/漏极区域的沟道区域和覆盖沟道区域的第二源极/漏极区域。 半导体柱的相对的侧壁不与栅电极或另一栅电极相邻。 还描述了半导体器件结构，形成垂直访问器件的方法以及形成半导体结构的方法。