公开(公告)号：US11990446B2

公开(公告)日：2024-05-21

申请号：US18094320

申请日：2023-01-06

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Madison E. Wale ,  James L. Voelz ,  Dylan W. Southern ,  Dustin L. Holloway

IPC: H01L23/00

CPC classification number: H01L24/82 ,  H01L24/20 ,  H01L24/29 ,  H01L24/45 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/82203 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly comprises a die stack including a plurality of semiconductor dies, and a routing substrate mounted on the die stack. The routing substrate includes an upper surface having a redistribution structure. The semiconductor assembly also includes a plurality of electrical connectors coupling the redistribution structure to at least some of the semiconductor dies. The semiconductor assembly further includes a controller die mounted on the routing substrate. The controller die includes an active surface that faces the upper surface of the routing substrate and is electrically coupled to the redistribution structure, such that the routing substrate and the semiconductor dies are electrically coupled to the controller die via the redistribution structure.

公开(公告)号：US11973062B2

公开(公告)日：2024-04-30

申请号：US18169735

申请日：2023-02-15

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Akshay N. Singh

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L21/60

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/49827 ,  H01L2021/60037

Abstract: A semiconductor device assembly can include a first semiconductor device and an interposer. The interposer can include a substrate and through vias in which individual vias include an exposed portion and an embedded portion, the exposed portions projecting from one or both of the first surface and the second surface of the substrate, and the embedded portions extending through at least a portion of the substrate. The interposer can include one or more test pads, a first electrical contact, and a second electrical contact. The semiconductor device assembly can include a controller positioned on an opposite side of the interposer from the first semiconductor device and operably coupled to the interposer via connection to the second electrical contact.

公开(公告)号：US11791315B2

公开(公告)日：2023-10-17

申请号：US17520568

申请日：2021-11-05

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay ,  Eiichi Nakano

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H05K1/02

CPC classification number: H01L25/0657 ,  H01L23/3738 ,  H01L23/49877 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H05K1/0207 ,  H01L2224/16235 ,  H01L2224/17519 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06589 ,  H05K2201/066 ,  H05K2201/10159

Abstract: Semiconductor assemblies including thermal layers and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise one or more semiconductor devices over a substrate. The substrate includes a thermal layer configured to transfer thermal energy across the substrate. The thermal energy is transferred from the semiconductor device to the graphene layer using one or more thermal connectors.

公开(公告)号：US20230187224A1

公开(公告)日：2023-06-15

申请号：US18106225

申请日：2023-02-06

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Chan H. Yoo

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L21/56 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114

Abstract: Methods for manufacturing semiconductor devices having a flexible reinforcement structure, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes electrically coupling at least one semiconductor die to a redistribution structure on a first carrier. The semiconductor die can include a first surface facing the redistribution structure and a second surface spaced apart from the redistribution structure. The method also includes reducing a thickness of the semiconductor die to no more than 10 μm. The method further includes coupling a flexible reinforcement structure to the second surface of the at least one semiconductor die.

公开(公告)号：US11664291B2

公开(公告)日：2023-05-30

申请号：US17115716

申请日：2020-12-08

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay

IPC: H01L23/36 ,  H01L23/42 ,  H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H05K7/20

CPC classification number: H01L23/36 ,  H01L23/42 ,  H01L23/49822 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H05K7/2039 ,  H01L2224/73204 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1434 ,  H05K2201/10378

Abstract: Semiconductor assemblies including thermal management configurations for reducing heat transfer between overlapping devices and associated systems and methods are disclosed herein. A semiconductor assembly may comprise a first device and a second device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the first and second devices. The thermally conductive layer and/or the thermal-insulator interposer may be configured to reduce heat transfer between the first and second devices.

公开(公告)号：US20230045144A1

公开(公告)日：2023-02-09

申请号：US17971889

申请日：2022-10-24

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Madison E. Wale ,  James L. Voelz ,  Dylan W. Southern

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/13 ,  H01L25/065 ,  H01L25/00

Abstract: Systems and methods for a semiconductor device having an edge-notched substrate are provided. The device generally includes a substrate having a front side, a backside having substrate contacts, and an inward notch at an edge of the substrate. The device includes a die having an active side attached to the front side of the substrate and positioned such that bond pads of the die are accessible from the backside of the substrate through the inward notch. The device includes wire bonds routed through the inward notch and electrically coupling the bond pads of the die to the substrate contacts. The device may further include a second die having an active side attached to the backside of the first die and positioned laterally offset from the first die such that the second bond pads are accessible by wire bonds around the edge of the first die and through the inward notch.

公开(公告)号：US20220375917A1

公开(公告)日：2022-11-24

申请号：US17881519

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.

公开(公告)号：US11476241B2

公开(公告)日：2022-10-18

申请号：US16805341

申请日：2020-02-28

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay

IPC: H01L25/18 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00

Abstract: An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.

公开(公告)号：US20220293569A1

公开(公告)日：2022-09-15

申请号：US17832019

申请日：2022-06-03

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay

IPC: H01L25/065 ,  H01L21/683 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L25/00

Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.

公开(公告)号：US11444067B2

公开(公告)日：2022-09-13

申请号：US16715242

申请日：2019-12-16

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Chan H. Yoo

IPC: H01L29/40 ,  H01L25/18 ,  H01L25/16 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

Abstract: An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.